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  • MAX17600数据资料

     The MAX17600–MAX17605 devices are high-speedMOSFET drivers capable of sinking /sourcing 4A peakcurrents. The devices have various inverting and noninvertingpart options that provide greater flexibility incontrolling the MOSFET. The devices have internal logiccircuitry that prevents shoot-through during output-statchanges. The logic inputs are protected against voltagespikes UP to +14V, regardless of VDD voltage. Propagationdelay time is minimized and matched between the dualchannels. The devices have very fast switching time,combined with short propagation delays (12ns typ),making them ideal for high-frequency circuits. Thedevices operate from a +4V to +14V single powersUPply and typically consume 1mA of sUPply current.The MAX17600/MAX17601 have standard TTLinput logic levels, while the MAX17603 /MAX17604/MAX17605 have CMOS-like high-noise margin (HNM)input logic levels. The MAX17600/MAX17603 are dualinverting input drivers, the MAX17601/MAX17604 aredual noninverting input drivers, and the MAX17602 /MAX17605 devices have one noninverting and oneinverting input. These devices are provided with enablepins (ENA, ENB) for better control of driver operation.

    标签: 17600 MAX 数据资料

    上传时间: 2013-12-20

    上传用户:zhangxin

  • 高精度I2C实时时钟的设计

    Abstract: This application note presents an overview of the operational characteristics of accurate I&sUP2;C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I&sUP2;C communication circuit configurations, and I&sUP2;C characteristics relative to device power-UP sequences andinitializations. Additional discussions on decoUPling are provided to sUPport developing strategies for mitigating power-sUPply pushingof device frequency.

    标签: I2C 高精度 实时时钟

    上传时间: 2013-11-23

    上传用户:WMC_geophy

  • 利用数字电位器调整并校准升压型DC-DC转换器

    The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-UP DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-UP DC-DC converter (capable of generating UP to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input sUPply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).

    标签: DC-DC 数字电位器 升压型 校准

    上传时间: 2014-12-23

    上传用户:781354052

  • 真有效值转换器的自动调节

      The LTC®1966 is a true RMS-to-DC converter that uses aDS computational technique to make it dramatically simplerto use, significantly more accurate, lower in powerconsumption and more flexible than conventional logantilogRMS-to-DC converters. The LTC1966 RMS-to-DCconverter has an input signal range from 5mVRMS to1.5VRMS (a 50dB dynamic range with a single 5V sUPplyrail) and a 3dB bandwidth of 800kHz with signal crestfactors UP to four.

    标签: 真有效值 转换器 自动调节

    上传时间: 2013-10-12

    上传用户:qilin

  • STM32F10xxx设备中如何得到高精度ADC

    The STM32F10xxx microcontroller family embeds UP to three advanced 12-bit ADCs (depending on the device) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.

    标签: STM 32F F10 ADC

    上传时间: 2014-12-23

    上传用户:eastimage

  • 寄生电容在升压变压器中的设计应用

    One of the most critical components in a step-UP design like Figure 1 is the transformer. Transformers have parasitic components that can cause them to deviate from their ideal characteristics, and the parasitic capacitance associated with the secondary can cause large resonating current spikes on the leading edge of the switch current waveform.

    标签: 寄生电容 升压变压器 中的设计

    上传时间: 2013-11-22

    上传用户:15070202241

  • ADC转换器技术用语 (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows UP as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset UP time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    标签: Converter Defi ADC 转换器

    上传时间: 2013-11-12

    上传用户:pans0ul

  • Active Filters

    Power conversion by virtue of its basic role produces harmonics due to theslicing of either voltages or currents. To a large extent the pollution in theutility sUPply and the deterioration of the power quality has been generatedor created by non-linear converters. It is therefore ironic that power convertersshould now be used to clean UP the pollution that they helped to create inthe first place.In a utility system, it is desirable to prevent harmonic currents (which resultin EMI and resonance problems) and limit reactive power flows (whichresult in transmission losses).Traditionally, shunt passive filters, comprised of tuned LC elements andcapacitor banks, were used to filter the harmonics and to compensate forreactive current due to non-linear loads. However, in practical applicationsthese methods have many disadvantages.

    标签: Filters Active

    上传时间: 2013-11-05

    上传用户:AISINI005

  • Creating Safe State Machines(Mentor)

      Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers UP in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.

    标签: Creating Machines Mentor State

    上传时间: 2013-10-08

    上传用户:wangzhen1990

  • Cadence 应用注意事项

    good good study ,day day UP

    标签: Cadence 注意事项

    上传时间: 2014-05-15

    上传用户:wvbxj