讲述未来无线通信soc的设计方法，要点和未来的发展趋势
上传时间： 2013-12-27
上传用户：xiaoyunyun
---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.
标签： Wishbone_BFM WISHBONE Wishbon Core
上传时间： 2016-09-04
上传用户：lanjisu111
i.mx27 soc for wince 6.0
上传时间： 2016-09-05
上传用户：xjz632
LCD Driver datasheet The SPF54126A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 176xRGBx220 in resolution which can be achieved by the designated RAM for graphic data. The 528-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The source driver of SPFD54126A adopts OP-AMP structure to enhance display quality and it cooperates with advanced circuitry techniques to reduce power consumption.
标签： System-on-Chip datasheet designed Driver
上传时间： 2016-09-22
上传用户：xauthu
ili9320 datasheet. ILI9320 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit.
标签： 9320 datasheet one-chip crystal
上传时间： 2014-11-21
上传用户：jiahao131
Linux uart driver for Infineon ADM5120 SOC Uart port. This is good reference to operate the SOC uart port.
标签： uart SOC reference Infineon
上传时间： 2016-09-26
上传用户：lgnf
V9001单相电能计量SoC提供单相电能表的单片解决方案，可以大幅简化电能表设计，降低系统成本，并缩短产品上市时间： 集成高精度Σ/ΔADC集成高精度，多功能电能计量DSP电路，集成高性能微控制器MCU
上传时间： 2014-12-22
上传用户：asdfasdfd
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
标签： Description Behavorial wb_master Filename
上传时间： 2014-07-11
上传用户：zhanditian
Introduce the wishbone bus .
标签： Introduce wishbone the bus
上传时间： 2013-11-28
上传用户：lacsx
用于SoC设计的DFT和BIST，讲解了在SOC设计中需要考虑的可测性设计问题
上传时间： 2016-10-28
上传用户：亚亚娟娟123
