介绍了基于单片机航空交流电参数测试仪的系统设计。以Silicon Labs公司的C8051F005单片机为核心设计出数据采集板，通过RS-232串口与上位机通讯。运用Lab Windows/CVI编写的上位机软件实现信号的检测以及波形和数据的显示，给出了测试仪硬件电路的组成和软件流程图。本系统具有硬件结构简单、容易实现和成本低等特点，在实际应用中其稳定性、精确性均能满足客户要求。 Abstract: The design of aeronautics AC parameters tester based on the single-chip is introduced.The core component of data acquisition board is C8051F005 single chip of Silicon Labs Company,and communication with PC through RS-232. The signal processing software programmed with LabWindows/CVI can be used successfully to fulfill inspection of signal and display of the waveform and data. The hardware and software configuration of test instrument are provided.The hardware of the system is simple, and can be easily realized.The stability and precision of the measurement instrument are enough to meet the requirements.
上传时间： 2013-11-18
上传用户：wang5829
随着单片机功能集成化的发展，其应用领域也逐渐地由传统的控制，扩展为控制处理、数据处理以及数字信号处理（DSP，Digital Signal Processing）等领域。凌阳的16位单片机就是为适应这种发展而设计的。它的CPU内核采用凌阳最新推出的µ’nSP™（Microcontroller and Signal Processor）16位微处理器芯片（以下简称µ’nSP™）。围绕µ’nSP™所形成的16位µ’nSP™系列单片机（以下简称µ’nSP™家族）采用的是模块式集成结构，它以µ’nSP™内核为中心集成不同规模的ROM、RAM和功能丰富的各种外设接口部件。
上传时间： 2013-11-07
上传用户：wpwpwlxwlx
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two examples use a PIC which has an 8 bit timer and either a comparator or an ADC, although it can be modified for use on a PIC which has only digital I/O. The Appendices have example code for the 16C662 (with comparator) and 16F877 (using the ADC). As the majority of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to model the individual elements of a DTMF Decoder IC.
上传时间： 2013-11-21
上传用户：zhaoke2005
SPCE061A采用的内核 SPCE061A采用的内核（CPU）为μ‘nSP。 μ‘nSP（读做micro-n-S-P）是凌阳科技推出的16位微处理器，它的突出特点是较高的处理速度，这就使其有能力进行复杂的数字信号处理（DSP，Digital Signal Processing）。 μ‘nSP内核由凌阳自主开发，因而也具备它自己的指令系统。 指令系统.61 3.1 指令系统的概述及符号约定.61 3.2 数据传送指令62 3.3 算术运算..66 3.3.1 加法运算..67 3.3.2 减法运算..68 3.3.3 带进位的加减运算.70 3.3.4 取补运算..70 3.3.5 SPCE061A的乘法指令.71 3.3.6 SPCE061A的n项内积运算指令.71 3.3.7 比较运算(影响标志位N,Z,S,C)..73 3.4 SPCE061A的逻辑运算.74 3.4.1 逻辑与..74 3.4.2 逻辑或..75 3.4.3 逻辑异或..76 3.4.4 测试（TEST）.78 3.4.5 SPCE061A的移位操作.80 3.5 SPCE061A的控制转移类指令..83 3.6 伪指令86 3.6.1 伪指令的语法格式及特点..87 3.6.2 伪指令符号约定..87 3.6.3 标准伪指令.87 3.6.4 宏定义与调用98 3.6.5 段的定义与调用101 3.6.6 结构的定义与调用..102 3.6.7 过程的定义与调用..106 3.6.8 伪指令的应用举例..106
上传时间： 2013-10-31
上传用户：xuanchangri
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上传时间： 2013-11-07
上传用户：swing
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上传时间： 2013-10-28
上传用户：15501536189
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-12
上传用户：kang1923
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
Mobile phones are constantly decreasing in size, thereby complicating the acoustical functionality. Signal processing methods can be used to partially mitigate this problem. In this paper we suggest a method which uses multiple spectral subtraction functions and two microphones, introducing only a short signal delay.
标签： functionality complicating acoustical constantly
上传时间： 2015-11-15
上传用户：youth25
The data files included are .MAT or *.dat (ASCII)files. The m-files and the data may be distributed, provided that the source is acknowledged in any publication and the data are not sold. Since this software is being distributed free of charge, the authors are not offering any technical support. Students who have any questions or difficulties using this software, or require the additional functions from the Signal Processing Toolbox should contact their professor.
标签： files data distributed The
上传时间： 2014-12-06
上传用户：wuyuying
