这一实验性的“餐馆系统”是一个很典型商业应用，但并不复杂。归根结底，就实现5个功能：1）增加一个新的预约（涉及数据库中的一个insert操作），2）删除一个被选中的预约（delete操作），3）在一个已有预约上记录到达时间（提前预约的顾客来吃饭了）（对应update操作），4）更改分配给一个预约的餐桌（update操作），5）显示指定日期内所有已有的预约（Select操作）。从数据库的角度来看，要实现这些功能不难。在我们的样板系统中，在运行时主要通过以下对象的合作，实现上述功能。
上传时间： 2018-11-02
上传用户：jack110
Introduction jSMPP is a java implementation (SMPP API) of the SMPP protocol (currently supports SMPP v3.4). It provides interfaces to communicate with a Message Center or an ESME (External Short Message Entity) and is able to handle traffic of 3000-5000 messages per second. jSMPP is not a high-level library. People looking for a quick way to get started with SMPP may be better of using an abstraction layer such as the Apache Camel SMPP component: http://camel.apache.org/smpp.html Travis-CI status: History The project started on Google Code: http://code.google.com/p/jsmpp/ It was maintained by uudashr on Github until 2013. It is now a community project maintained at http://jsmpp.org Release procedure mvn deploy -DperformRelease=true -Durl=https://oss.sonatype.org/service/local/staging/deploy/maven2/ -DrepositoryId=sonatype-nexus-staging -Dgpg.passphrase=<yourpassphrase> log in here: https://oss.sonatype.org click the 'Staging Repositories' link Select the repository and click close Select the repository and click release License Copyright (C) 2007-2013, Nuruddin Ashr uudashr@gmail.com Copyright (C) 2012-2013, Denis Kostousov denis.kostousov@gmail.com Copyright (C) 2014, Daniel Pocock http://danielpocock.com Copyright (C) 2016, Pim Moerenhout pim.moerenhout@gmail.com This project is licensed under the Apache Software License 2.0.
上传时间： 2019-01-25
上传用户：dragon_longer
The past decade has seen an explosion of machine learning research and appli- cations; especially, deep learning methods have enabled key advances in many applicationdomains,suchas computervision,speechprocessing,andgameplaying. However, the performance of many machine learning methods is very sensitive to a plethora of design decisions, which constitutes a considerable barrier for new users. This is particularly true in the booming field of deep learning, where human engineers need to Select the right neural architectures, training procedures, regularization methods, and hyperparameters of all of these components in order to make their networks do what they are supposed to do with sufficient performance. This process has to be repeated for every application. Even experts are often left with tedious episodes of trial and error until they identify a good set of choices for a particular dataset.
标签： Auto-Machine-Learning-Methods-Sys tems-Challenges
上传时间： 2020-06-10
上传用户：shancjb
%this is an example demonstrating the Radial Basis Function %if you Select a RBF that supports it (Gausian, or 1st or 3rd order %polyharmonic spline), this also calculates a line integral between two %points.
上传时间： 2021-07-02
上传用户：19800358905
FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip Select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip Select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
上传用户：
SH367309是5-16串锂电池BMS用数字前端芯片，适用于总电压不超过70V的锂电池Pack。 SH367309工作在保护模式下，可独立保护锂电池Pack。提供过充电保护、过放电保护、温度保护、充放电过流保护、短路保护、二次过充电保护等。集成平衡开关提高电芯一致性。 SH367309工作在采集模式下，可配合MCU管理锂电池Pack，同时使能所有保护功能。 SH367309内置VADC，用于采集电芯电压、温度以及电流；内置CADC采集电流，用于统计Pack剩余容量；内置EEPROM，用于保存保护阈值及延时等可调参数；内置TWI通讯接口，用于操作相关寄存器及EEPROM。产品特性介绍■ 硬件保护功能 - 过充电保护功能 - 过放电保护功能 - 充放电高温保护功能 - 充放电低温保护功能 - 充放电过流保护功能 - 短路保护功能 - 二次过充电保护功能 - 断线保护功能■ 内置平衡开关■ 禁止低压电芯充电功能■ 小电流检测功能■ 支持乱序上下电■ 内置看门狗模块■ 模式设计 - 采集模式（SH367309配合MCU应用） - 保护模式（SH367309独立应用） - 仓运模式 - 烧写模式■ 13-bit VADC用于采集电压/温度/电流 - 转换频率：10Hz - 16路电压采集通道 - 1路电流采集通道 - 3路温度采集通道■ 16-bit Ʃ-∆CADC用于采集电流 - 转换频率：4Hz■ 内置EEPROM - 编程/擦除次数：≤ 100次■ 稳压电源 - 3.3V（25mA@MAX）■ MOSFET驱动：电池组负端NMOS驱动■ CTL管脚：优先控制充放电MOSFET关闭■ TWI通讯接口：支持CRC8校验■ 低功耗设计： - IDLE状态 - SLEEP状态 - Powerdown状态■ 封装 - TQFP48L
标签： sh367309
上传时间： 2021-11-22
上传用户：jason_vip1
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip Select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
上传用户：
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip Selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
上传用户：
PW4203 is a 4.5-22V input, 2A multi-cell synchronous Buck Li-Ion battery charger, suitable forportable application. Select pin is convenient for multi-cell charging. 800 kHz synchronous buckregulator integrates of 22V rating FETs with ultra low on- resistance to achieve high efficiency andsimple circuit design.The PW4203 is available in an 8-pin SOP package, provides a very compact system solution andgood thermal conductance
标签： pw4203
上传时间： 2022-02-11
上传用户：
数字示波器功能强大,使用方便,但是价格相对昂贵。本文以Ti的MSP430F5529为主控器,以Altera公司的EP2C5T144C8 FPGA器件为逻辑控制部件设计数字示波器。模拟信号经程控放大、整形电路后形成方波信号送至FPGA测频,根据频率值选择采用片上及片外高速AD分段采样。FPGA控制片外AD采样并将数据输入到FIFO模块中缓存,由单片机进行频谱分析。测试表明:简易示波器可以实现自动选档、多采样率采样、高精度测频及频谱分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to Select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain Selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
上传时间： 2022-03-27
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