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SPECIFICATIONs-High

  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    标签: Transceiver Virtex Wizar GTP

    上传时间: 2013-10-23

    上传用户:leyesome

  • XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

      The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.

    标签: PCI-X XAPP DIMM 708

    上传时间: 2013-11-24

    上传用户:18707733937

  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    标签: Transceiver Virtex Wizar GTP

    上传时间: 2013-10-20

    上传用户:dave520l

  • pci e PCB设计规范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    标签: pci PCB 设计规范

    上传时间: 2014-01-24

    上传用户:s363994250

  • Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, whic

    Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable across platforms and network types

    标签: cross-platform developers abstract library

    上传时间: 2015-01-14

    上传用户:ghostparker

  • High Performance MySQL (O Reilly,2004)

    High Performance MySQL (O Reilly,2004)

    标签: Performance Reilly MySQL High

    上传时间: 2015-02-21

    上传用户:nanfeicui

  • NTL is a high-performance, portable C++ library providing data structures and algorithms for manipul

    NTL is a high-performance, portable C++ library providing data structures and algorithms for manipulating signed, arbitrary length integers, and for vectors, matrices, and polynomials over the integers and over finite fields.

    标签: high-performance algorithms structures providing

    上传时间: 2014-01-05

    上传用户:水中浮云

  • FlexCompress is a high-speed compression library developed to provide archive functionality for your

    FlexCompress is a high-speed compression library developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption algorithms that allows you to integrate archiving or backup features into your programs in a fast and easy way.

    标签: functionality FlexCompress compression high-speed

    上传时间: 2015-04-04

    上传用户:s363994250

  • SR-tree is an index structure for high-dimensional nearest neighbor queries

    SR-tree is an index structure for high-dimensional nearest neighbor queries,C++ sourcecode. SR-tree outperforms the R*-tree and the SS-tree especially for high-dimensional and non-uniform data which are likely to appear in the actual image / video applications.

    标签: high-dimensional structure neighbor SR-tree

    上传时间: 2013-12-10

    上传用户:zjf3110

  • A high quality VC++ source code implementing the very important context-based adaptive arithmetic co

    A high quality VC++ source code implementing the very important context-based adaptive arithmetic coder.

    标签: context-based implementing arithmetic important

    上传时间: 2015-04-10

    上传用户:changeboy