Altium Designer10软件+视频教程+常用元器件原理图库+常用PCB库下载地址： http://pan.baidu.com/SHARE/link?SHAREid=463765&uk=572810838 欢迎大家加入电子爱好者群 286744774。
上传时间： 2013-10-14
上传用户：yt1993410
This ink marks LTC’s eighth circuit collection publication.1We are continually surprised, to the point of near mystification, by these circuit amalgams seemingly limitlessappeal. Reader requests ascend rapidly upon publication,remaining high for years, even decades. All LTC circuitcollections, despite diverse content, SHARE this popularity,although just why remains an open question. Why isit? Perhaps the form; compact, complete, succinct andinsular. Perhaps the freedom of selection without commitment,akin to window shopping.
上传时间： 2014-01-06
上传用户：ligi201200
为了改变目前电网现场作业管理的变电巡检、变电检修试验、输电线路巡检检修等管理系统各自独立运行，信息不能共享，功能、效率受限，建设和维护成本高的现状，提出了采用B/S+C/S构架模式，将各现场作业管理模块和生产MIS（管理系统）集成为一体的现场作业管理系统的设计方案，做到各子系统和生产MIS软硬资源共享，做到同一数据唯一入口、一处录入多处使用。各子系统设备人员等基础信息来源于生产管理系统，各子系统又是生产管理系统的作业数据、缺陷信息的重要来源。经过研究试用成功和推广应用，目前该系统已在江西电网220 kV及以上变电站全面应用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t SHARE the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and SHARE the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
上传时间： 2013-11-15
上传用户：han_zh
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical prioritySHARE CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上传时间： 2013-10-13
上传用户：13162218709
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can SHARE a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：liu999666
目录 一、Smart Phone Market SHARE 1.1、中国智能手机销售量与变化状况 1.2、智能手机操作系统份额走势 1.3、智能手机销售价格走势 二、展讯智能手机方案 三、TI 无线充电方案 四、Freescale G+M二合一 Sensor 五、NXP NFC 六、TI 五合一 无线芯片 展讯智能手机方案框图
上传时间： 2014-12-30
上传用户：blacklee
Altium Designer10软件+视频教程+常用元器件原理图库+常用PCB库下载地址： http://pan.baidu.com/SHARE/link?SHAREid=463765&uk=572810838 欢迎大家加入电子爱好者群 286744774。
上传时间： 2013-11-21
上传用户：66666
怎样使用Nios II处理器来构建多处理器系统 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that SHARE Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上传时间： 2013-11-21
上传用户：lo25643
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can SHARE a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：aeiouetla
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel SHARE the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
