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SCALE

  • 基于DSP的永磁同步电机新型矢量控制技术研究.rar

    应用于电动汽车驱动领域的永磁同步电机交流驱动系统是由永磁同步电机、电力电子技术和控制技术相结合而形成的新型交流驱动系统。因其具有良好的运行性能而成为当代电气传动领域研究的热点之一。 永磁同步电机是一个多变量、非线性、高强耦合的系统,其输出转矩与定子电流不成正比,而是复杂的函数关系,因此要得到好的控制性能,需要进行磁场解耦。矢量变换控制技术正好适用于永磁同步电机的这种特点。 本文在数字电机控制专用DSP芯片TMS320LF2407的基础上,以永磁同步电机为研究对象,对其矢量控制技术进行了研究和设计。 首先课题根据永磁同步电机实际物理模型,分析推导得到了永磁同步电机的三相静止坐标系下及两相旋转坐标系下的数学模型。 接着课题对永磁同步电机运行特性进行了分析和研究。在此基础上,课题提出了一种新型的永磁同步电机矢量控制系统,在这个系统上,课题提出了应用不同矢量控制策略的矢量控制方法,并对其做了仿真验证。 结果表明,课题设计的系统以及应用不同矢量控制策略的矢量控制方法准确可行。 这个控制系统便于实现多种矢量控制方法,为永磁同步电机扩速增效提供了理论平台。 在理论分析、仿真通过基础上,课题对驱动系统的硬件和软件两个方面进行了具体的设计。 课题完成了DSP控制系统关键硬件电路的设计,并设计制作了一块应用SCALE模块的IGBT驱动电路,此驱动电路响应迅速、抗干扰性强,驱动性能优越。此外,课题完成了永磁同步电机矢量控制系统全数字化设计,调试通过了速度位置检测、电流检测、PI调节、坐标变换等应用模块。 课题最后对整个系统的做了全面的总结,并对今后的工作方向进行了展望。

    标签: DSP 永磁同步电机 技术研究

    上传时间: 2013-06-22

    上传用户:firstbyte

  • 一种基于SIFT描述子的特征匹配新算法

    为了克服传统的局部特征匹配算法对噪声和图像灰度非线性变换敏感的不足,提出了基于SIFT(SCALE Invariant Feature Transform)描述算子的特征匹配算法。该算法首先

    标签: SIFT 特征匹配 新算法

    上传时间: 2013-04-24

    上传用户:hphh

  • 精密DAC和看门狗提高模拟输出安全

    Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-SCALE (or pin-programmable midSCALE) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.

    标签: DAC 精密 看门狗 模拟

    上传时间: 2013-10-17

    上传用户:sjb555

  • DAC技术用语 (D/A Converters Defini

    Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full SCALE. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full SCALE Error): The difference between theoutput voltage (or current) with full SCALE input code and theideal voltage (or current) that should exist with a full SCALE inputcode.Gain Temperature Coefficient (Full SCALE TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full SCALE).Can be expressed as a percentage of full SCALE or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full SCALE voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.

    标签: Converters Defini DAC

    上传时间: 2013-10-30

    上传用户:stvnash

  • ADC转换器技术用语 (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full SCALE input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero SCALE Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    标签: Converter Defi ADC 转换器

    上传时间: 2013-11-12

    上传用户:pans0ul

  • 数字与模拟电路设计技巧

    数字与模拟电路设计技巧IC与LSI的功能大幅提升使得高压电路与电力电路除外,几乎所有的电路都是由半导体组件所构成,虽然半导体组件高速、高频化时会有EMI的困扰,不过为了充分发挥半导体组件应有的性能,电路板设计与封装技术仍具有决定性的影响。 模拟与数字技术的融合由于IC与LSI半导体本身的高速化,同时为了使机器达到正常动作的目的,因此技术上的跨越竞争越来越激烈。虽然构成系统的电路未必有clock设计,但是毫无疑问的是系统的可靠度是建立在电子组件的选用、封装技术、电路设计与成本,以及如何防止噪讯的产生与噪讯外漏等综合考虑。机器小型化、高速化、多功能化使得低频/高频、大功率信号/小功率信号、高输出阻抗/低输出阻抗、大电流/小电流、模拟/数字电路,经常出现在同一个高封装密度电路板,设计者身处如此的环境必需面对前所未有的设计思维挑战,例如高稳定性电路与吵杂(noisy)性电路为邻时,如果未将噪讯入侵高稳定性电路的对策视为设计重点,事后反复的设计变更往往成为无解的梦魇。模拟电路与高速数字电路混合设计也是如此,假设微小模拟信号增幅后再将full SCALE 5V的模拟信号,利用10bit A/D转换器转换成数字信号,由于分割幅宽祇有4.9mV,因此要正确读取该电压level并非易事,结果造成10bit以上的A/D转换器面临无法顺利运作的窘境。另一典型实例是使用示波器量测某数字电路基板两点相隔10cm的ground电位,理论上ground电位应该是零,然而实际上却可观测到4.9mV数倍甚至数十倍的脉冲噪讯(pulse noise),如果该电位差是由模拟与数字混合电路的grand所造成的话,要测得4.9 mV的信号根本是不可能的事情,也就是说为了使模拟与数字混合电路顺利动作,必需在封装与电路设计有相对的对策,尤其是数字电路switching时,ground vance noise不会入侵analogue ground的防护对策,同时还需充分检讨各电路产生的电流回路(route)与电流大小,依此结果排除各种可能的干扰因素。以上介绍的实例都是设计模拟与数字混合电路时经常遇到的瓶颈,如果是设计12bit以上A/D转换器时,它的困难度会更加复杂。

    标签: 数字 模拟电路 设计技巧

    上传时间: 2013-11-16

    上传用户:731140412

  • 基于UC3854A控制的PFC中分岔现象仿真研究

       为深入了解基于UC3854A控制的PFC变换器中的动力学特性,研究系统参数变化对变换器中分岔现象的影响,在建立Boost PFC变换器双闭环数学模型的基础上,用Matlab软件对变换器中慢时标分岔及混沌等不稳定现象进行了仿真。在对PFC变换器中慢时标分岔现象仿真的基础上,分析了系统参数变化对分岔点的影响,并进行了仿真验证。仿真结果清晰地显示了输入整流电压的幅值变化对系统分岔点的影响。 Abstract:  In order to better understand the dynamics characteristic of power factor correction converter based on UC3854A, and make the way that parameters change influences the bifurcation phenomena of the system clearly. The math model of the two closed loop circuits to the Boost PFC (Power Factor Correction) converter controller was built. Then, with the help of Matlab, the simulation for nonlinear phenomena such as chaos and slow-SCALE bifurcation in the PFC converter was made. Finally the factors that have influence to the phenomenon of bifurcation under slow-SCALE in PFC converter were analyzed. The simulation results clearly show the parameters change influences the bifurcation point of the system.

    标签: 3854A 3854 PFC UC

    上传时间: 2013-10-17

    上传用户:杜莹12345

  • 《器件封装用户向导》赛灵思产品封装资料

    Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-SCALE functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.

    标签: 封装 器件 用户 赛灵思

    上传时间: 2013-10-22

    上传用户:ztj182002

  • 《器件封装用户向导》赛灵思产品封装资料

    Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-SCALE functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.

    标签: 封装 器件 用户 赛灵思

    上传时间: 2013-11-21

    上传用户:不懂夜的黑

  • 数字与模拟电路设计技巧

    数字与模拟电路设计技巧IC与LSI的功能大幅提升使得高压电路与电力电路除外,几乎所有的电路都是由半导体组件所构成,虽然半导体组件高速、高频化时会有EMI的困扰,不过为了充分发挥半导体组件应有的性能,电路板设计与封装技术仍具有决定性的影响。 模拟与数字技术的融合由于IC与LSI半导体本身的高速化,同时为了使机器达到正常动作的目的,因此技术上的跨越竞争越来越激烈。虽然构成系统的电路未必有clock设计,但是毫无疑问的是系统的可靠度是建立在电子组件的选用、封装技术、电路设计与成本,以及如何防止噪讯的产生与噪讯外漏等综合考虑。机器小型化、高速化、多功能化使得低频/高频、大功率信号/小功率信号、高输出阻抗/低输出阻抗、大电流/小电流、模拟/数字电路,经常出现在同一个高封装密度电路板,设计者身处如此的环境必需面对前所未有的设计思维挑战,例如高稳定性电路与吵杂(noisy)性电路为邻时,如果未将噪讯入侵高稳定性电路的对策视为设计重点,事后反复的设计变更往往成为无解的梦魇。模拟电路与高速数字电路混合设计也是如此,假设微小模拟信号增幅后再将full SCALE 5V的模拟信号,利用10bit A/D转换器转换成数字信号,由于分割幅宽祇有4.9mV,因此要正确读取该电压level并非易事,结果造成10bit以上的A/D转换器面临无法顺利运作的窘境。另一典型实例是使用示波器量测某数字电路基板两点相隔10cm的ground电位,理论上ground电位应该是零,然而实际上却可观测到4.9mV数倍甚至数十倍的脉冲噪讯(pulse noise),如果该电位差是由模拟与数字混合电路的grand所造成的话,要测得4.9 mV的信号根本是不可能的事情,也就是说为了使模拟与数字混合电路顺利动作,必需在封装与电路设计有相对的对策,尤其是数字电路switching时,ground vance noise不会入侵analogue ground的防护对策,同时还需充分检讨各电路产生的电流回路(route)与电流大小,依此结果排除各种可能的干扰因素。以上介绍的实例都是设计模拟与数字混合电路时经常遇到的瓶颈,如果是设计12bit以上A/D转换器时,它的困难度会更加复杂。

    标签: 数字 模拟电路 设计技巧

    上传时间: 2014-02-12

    上传用户:wenyuoo