利用LWIP做的STM32的网口程序，这是ST公司提供的官方例程
标签： lwIP
上传时间： 2019-07-02
上传用户：zycmic
用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看
上传时间： 2019-12-06
上传用户：木瓜呱呱呱
ALIENTEK 战舰ENC28J60 LWIP和UIP补充例程
上传时间： 2021-09-22
上传用户：stf1983
lwip适配gd32协议栈，已应用于gd32 303 MCU上。
上传时间： 2021-09-24
上传用户：linuxp
前不久接到一个客户的问题。在 H743 上需要通过 UDP 发送大的数据包，涉及到 IP 分包的问题。他们在测试的过程中遇到了 只要发送 6KB 的 UDP 数据包就会出现 hardfault 的问题。拿到这个问题的时候，调试得到了和客户一样的现象，程序进入 hardfault，并且是由 Lwip 协议栈的 ip_reass_free_complete_datagram 函数触发。后经过一番调试，搞清楚了问题的原 因，要说清楚，我们得先来看看 Lwip 中 IP 分包的实现
上传时间： 2022-03-06
上传用户：
嵌入式TCPIP协议栈LWIP的并发性能优化共66页这是一份非常不错的资料，欢迎下载，希望对您有帮助！
上传时间： 2022-03-10
上传用户：slq1234567890
基于FreeRTOS的lwip协议栈的移植与测试
上传时间： 2022-03-20
上传用户：qingfengchizhu
电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
该文档为利用SystemverilogUVM搭建SOC及ASIC的RTL的验证环境讲解文档，是一份很不错的参考资料，具有较高参考价值，感兴趣的可以下载看看………………
上传时间： 2022-04-12
上传用户：
网络实验2 LWIP带UCOS操作系统移植
上传时间： 2022-04-19
上传用户：
