数字秒表的设计，RESET为归零设置，start为重新计时设置
标签： 数字秒表
上传时间： 2013-12-12
上传用户：xieguodong1234
D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 220h-240h is transfered to 240h-260h using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are RESET to inital software setting because DMA transfer mode 5 is used. P1.0 is toggled durring DMA transfer only for demonstration purposes. ** RAM location 0x220 - 0x260 used - always make sure no compiler conflict ** ACLK= n/a, MCLK= SMCLK= default DCO ~ 800k
标签： Description Repeated Software to-from
上传时间： 2014-01-09
上传用户：thinode
CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous RESET
标签： polynomial Features Executes clock
上传时间： 2013-12-18
上传用户：Ants
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and RESET controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
标签： diffusion-limited-aggregation DLA generates 320x240
上传时间： 2014-01-16
上传用户：225588
linux下同一个进程中多个定时器实现。简单描述下定时器模块的实现，有一个manager单例类保存所有CTimer对象，开启一线程运行延迟函数，每次延迟间隔到，扫描保存CTimer的容器，对每个CTimer对象执行减少时间操作，减少到0则执行回调函数。对一次性CTimer，超时则从容器中删除，循环型的将间隔时间重置，不从容器中移除。 CTimer的start执行将对象插入到manager容器中操作；stop执行将对象从manager容器中删除的操作；RESET执行先删除，重置间隔，然后再放到容器中，RESET不改变CTimer的定时器类型属性。 代码来源于CppExplore，感谢博客主的共享。
上传时间： 2017-01-03
上传用户：daguda
/* 线路图 89C51 T6963C -------- | 8 P1.0-1.7|=========== D0-7 | P3.0|----------- /RD P3.1|----------- /WR P3.2|----------- C/D | -- /CE | | | --- P3.3|----------- /RESET | VCC--- /HALT -------- */
上传时间： 2013-12-20
上传用户：集美慧
DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters. In addition to 1W nominal galvanically isolated output power capability, the range of DC/DCs are also fully synchronizable. The devices feature thermal shutdown, and overload protection is implemented via watchdog circuitry. Advanced power-on RESET techniques give superior RESET performance and the devices will start into any capacitive load up to full power output. The DCP0105 family is implemented in standard- molded IC packaging, giving outlines suitable for high volume assembly.
标签： DESCRIPTION efficiency converters isolated
上传时间： 2013-11-28
上传用户：CHENKAI
伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）
上传时间： 2014-12-03
上传用户：小宝爱考拉
管脚号 管脚名称 LEVER 管脚功能描述 1 VSS 0V 电源地 2 VDD 5.0V 电源电压 3 VEE 5.0V~(-13V) 液晶显示器驱动电压 4 D/I H/L D/I=“H”,表示DB7~DB0为显示数据 D/I=“L”,表示DB7~DB0为显示指令数据 5 R/W H/L R/W=“H”,E=“H”,数据被读到DB7~DB0 R/W=“L”,E=“H→L”, DB7~DB0的数据被写到IR或DR 6 E H/L 使能信号：R/W=“L”,E信号下降沿锁存DB7~DB0 R/W=“H”,E=“H” DRAM数据读到DB7~DB0 7 DB0 H/L 数据线 8 DB1 H/L 数据线 9 DB2 H/L 数据线 10 DB3 H/L 数据线 11 DB4 H/L 数据线 12 DB5 H/L 数据线 13 DB6 H/L 数据线 14 DB7 H/L 数据线 15 CS1 L （19264A) 选择IC1,即（左）64列 16 RESET L 复位控制信号，RST=0有效 17 CS2 L （19264A) 选择IC2,即（中）64列 18 CS3 L （19264A) 选择IC3,即（右）64列 19 V0 -9V Negative Voltage for LCD driving 20 LED+ +5.0V The LED supply
上传时间： 2014-01-01
上传用户：541657925
The MINI2440 is an effecient ARM9 development board with a comprehensive price, it characterizes simple method and high performance-price ratio. Based on the Samsung S3C2440 microprocessor, it embodies professional stable CPU core power source chip and RESET chip to ensure the stability of the system operation. The PCB on the MINI2440 board is designed to be 4-layers board, adopting the ENIG technology and professional equal-length wiring to ensure the completeness of the signals of the key signal wires and manufactured and released under stringent quality control plans. With the help of this detailed manual, users are supposed to become proficient in the development process of embedded Linux and WinCE operating system, they are supposed to get the foundation, so long as they have obtained the basic and necessary knowledge about the C language, in two weeks.
标签： comprehensive characterizes development effecient
上传时间： 2013-12-18
上传用户：csgcd001
