this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the Processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
标签： implementation include quartus source
上传时间： 2013-12-25
上传用户：坏坏的华仔
很全的中断手册。 INT 00 - CPU-generated - DIVIDE ERROR INT 01 - CPU-generated - SINGLE STEP (80386+) - DEBUGGING EXCEPTIONS INT 02 - external hardware - NON-MASKABLE INTERRUPT INT 03 - CPU-generated - BREAKPOINT INT 04 - CPU-generated - INTO DETECTED OVERFLOW INT 05 - PRINT SCREEN CPU-generated (80186+) - BOUND RANGE EXCEEDED INT 06 - CPU-generated (80286+) - INVALID OPCODE INT 07 - CPU-generated (80286+) - Processor EXTENSION NOT AVAILABLE INT 08 - IRQ0 - SYSTEM TIMER CPU-generated (80286+) . . .
标签： CPU-generated INT DIVIDE SINGLE
上传时间： 2013-12-27
上传用户：aa54
This document is an operation guide for the MPC8XXFADS board. It contains operational, functional and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/ w and h/w development around the MPC8XX family Processors. Using its on-board resources and its associated debugger, a developer is able to download his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a desired system with the MPC8XX Processor.
标签： operational MPC8XXFADS functional operation
上传时间： 2014-03-10
上传用户：zsjinju
自20世纪70年代初到现在，并行计算机的发展已有20多年的历史.在此期间，出现了各种不同类型的并行机，包括历史上曾经风行一时的并行向量机PVP(Parallel Vector Processor)和SIMD 计算机，但它们现在均已衰落了下来
标签：
上传时间： 2016-02-20
上传用户：lili123
=== === === === === === === === === === ==== IBM PC KEYBOARD INFORMATION FOR SOFTWARE DEVELOPERS ================================================================ Sources: PORTS.A of Ralf Brown s interrupt list collection repairfaq.org keyboard FAQ(doesn t appear to exsist) Linux source code Test hardware: New Samsung KB3T001SAXAA 104-key keyboard Old Maxi 2186035-00-21 101-key keyboard NO WARRANTY. NO GUARANTEE. I have tried to make this information accurate. I don t know if I succeeded. Corrections or additional information would be welcome. This is a plain-text document. If you use a word-Processor to view it, use a fixed-pitch font (like Courier) so columnar data and ASCII art lines up properly.
标签： INFORMATION DEVELOPERS KEYBOARD SOFTWARE
上传时间： 2014-08-18
上传用户：ecooo
This the source release kit for the following system configuration(s): - AMD Alchemy(TM) DBAu1200(TM) and AMD Alchemy(TM) Pb1200(TM) development boards (AMD Alchemy(TM) Au1200(TM) Processor) - Windows CE 5.0 - RMI Au1200 Core BSP v1.51 - RMI Au1200 Media BSP v1.51
标签： configuration the following Alchemy
上传时间： 2014-02-21
上传用户：lps11188
SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC Processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
标签： high-level following reference diagram
上传时间： 2013-12-15
上传用户：Miyuki
tda7412的资料，CARRADIO SIGNAL Processor，I2C-BUS INTERFACE
上传时间： 2016-03-04
上传用户：lanhuaying
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s Processor bus, providing faster data transfers between the Processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system Processor. It represents the first microProcessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.
标签： bottleneck developed the concept
上传时间： 2014-12-03
上传用户：ikemada
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s Processor bus, providing faster data transfers between the Processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system Processor. It represents the first microProcessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video. Hardware reference
标签： bottleneck developed the concept
上传时间： 2016-03-18
上传用户：极客
