基于AT89C52单片机的步进电机控制系统设计 摘 要: 提出了一个由AT89C52单片机控制步进电机的实例。可以通过键盘输入相关数据, 并根据需要, 实时对步进电机工作方式进行设置, 具有实时性和交互性的特点。该系统可应用于步进电机控制的大多数场合。实践表明, 系统性能优于传统的步进电机控制器。 关键词: 单片机; 步进电动机; 直流固态继电器; 实时控制 ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the PeRFormance of this system outdid the tradi-tional stepp ing motor controller.
上传时间： 2013-11-22
上传用户：vodssv
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized PeRFormance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
上传时间： 2013-11-09
上传用户：geshaowei
MC9S08QG8英文资料 The MC9S08QG8 is the newest member of the Freescale 8-bit family of highly integratedmicrocontrollers, based on the high-PeRFormance yet low power HCS08 core. The MC9S08QG8is an excellent solution for power-sensitive applications with extended battery life and maximum PeRFormance down to 1.8VDC.
上传时间： 2014-12-28
上传用户：dxxx
Luminary Micro provides an analog-to-digital converter (ADC) module on some members of theStellaris microcontroller family. The hardware resolution of the ADC is 10 bits; however, due to noiseand other accuracy-diminishing factors, the true accuracy is less than 10 bits. This application noteprovides a software-based oversampling technique, resulting in an improved Effective Number OfBits (ENOB) in the conversion result. This document describes methods of oversampling an inputsignal, and the impact on precision and overall system PeRFormance.
标签： Oversampling Techniques ADC fo
上传时间： 2013-12-17
上传用户：zhyiroy
基于单片机的除尘控制器的设计:介绍通用控制仪的硬件组成和软件设计,阐述了系统的性能指标和功能特点。该产品功能完善,可靠性高,具有很好的应用前景。关键词: 除尘器;通用控制仪;单片机;系统设计 Abstract: The hardware structure and the software design are introduced in this paper, and the PeRFormance index and the features of the system are expounded. It has comp rehensive functions, high reliability and good app lication.Key words: dust catcher; universal controller; microcontroller; system design
上传时间： 2013-11-16
上传用户：ming52900
文章提出了一种精简指令集8 位单片机中, 算术逻辑单元的工作原理。在此基础上, 对比传统PIC 方案、以及在ALU 内部再次采用流水线作业的332 方案、44 方案, 并用Synopsys 综合工具实现了它们。综合及仿真结果表明, 根据该单片机系统要求, 44 方案速度最高, 比332 方案可提高43.9%, 而面积仅比最小的332 方案增加1.6%。在分析性能差异的根本原因之后, 阐明了该方案的优越性。关键词: 单片机, 精简指令集, 算术逻辑单元, 流水线 Abstract: Work principle for ALU in an 8_bit RISC Singlechip microcomputer is described. The traditional PIC scheme, 332 Pipeline scheme and 44 Pipeline scheme are compared on the base of the principle, which are implemented using Synopsys design tools. Results from synthesis and simulation shows that 44 scheme operates the fast, which is 43.9% faster and only 1.6% larger than 332 scheme. The essential reason why the PeRFormance is so different is analyzed.Then the advantage of 44 scheme is clarified.Key words: Singlechip, Microcomputer, RISC, ALU, Pipeline
上传时间： 2013-10-18
上传用户：xiaoyaa
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a PeRFormance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this PeRFormance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted PeRFormance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUPeRFormance required by software for emulating the SSC.
标签： synchronous Emulating serial
上传时间： 2014-01-31
上传用户：z1191176801
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-PeRFormance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high PeRFormance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high PeRFormance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
上传时间： 2013-11-10
上传用户：liaofamous
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-PeRFormance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上传时间： 2013-11-19
上传用户：shirleyYim
