多远程二极管温度传感器-Design Considerations for pc thermal management Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product performance and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall performance of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-PROGRAMmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
标签： Considerat Design 远程 二极管
上传时间： 2014-12-21
上传用户：ljd123456
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-PROGRAMmable gate array (FPGA).
上传时间： 2014-12-22
上传用户：xanxuan
Abstract: Field-PROGRAMmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signalprocessing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs.It also discusses Maxim's solutions for powering Xilinx® FPGAs.
上传时间： 2013-12-16
上传用户：haohaoxuexi
介绍了SoPC（System on a PROGRAMmable Chip）系统的概念和特点，给出了基于PLB总线的异步串行通信（UART）IP核的硬件设计和实现。通过将设计好的UART IP核集成到SoPC系统中加以验证，证明了所设计的UART IP核可以正常工作。该设计方案为其他基于SoPC系统IP核的开发提供了一定的参考。
上传时间： 2013-11-12
上传用户：894448095
Xilinx UltraScale™ 架构针对要求最严苛的应用，提供了前所未有的ASIC级的系统级集成和容量。 UltraScale架构是业界首次在All PROGRAMmable架构中应用最先进的ASIC架构优化。该架构能从20nm平面FET结构扩展至16nm鳍式FET晶体管技术甚至更高的技术，同 时还能从单芯片扩展到3D IC。借助Xilinx Vivado®设计套件的分析型协同优化，UltraScale架构可以提供海量数据的路由功能，同时还能智能地解决先进工艺节点上的头号系统性能瓶颈。 这种协同设计可以在不降低性能的前提下达到实现超过90%的利用率。 UltraScale架构的突破包括： • 几乎可以在晶片的任何位置战略性地布置类似于ASIC的系统时钟，从而将时钟歪斜降低达50% • 系统架构中有大量并行总线，无需再使用会造成时延的流水线，从而可提高系统速度和容量 • 甚至在要求资源利用率达到90%及以上的系统中，也能消除潜在的时序收敛问题和互连瓶颈 • 可凭借3D IC集成能力构建更大型器件，并在工艺技术方面领先当前行业标准整整一代 • 能在更低的系统功耗预算范围内显著提高系统性能，包括多Gb串行收发器、I/O以及存储器带宽 • 显著增强DSP与包处理性能 赛灵思UltraScale架构为超大容量解决方案设计人员开启了一个全新的领域。
标签： UltraScale Xilinx 架构
上传时间： 2013-12-23
上传用户：小儒尼尼奥
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All PROGRAMmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/PROGRAMmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and PROGRAMmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-14
上传用户：zoudejile
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-PROGRAMmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
标签： PicoBlaze Create Master Xilinx
上传时间： 2013-11-12
上传用户：大三三
Designing withPROGRAMmable Logicin an Analog WorldPROGRAMmable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex PROGRAMmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
标签： Solutions Analog Xilinx FPGAs
上传时间： 2013-11-07
上传用户：suicone
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. PROGRAMmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上传时间： 2014-01-11
上传用户：a471778
