RT7273是一颗完全跟TPS65251 PIN TO PIN 替换料号,一路进三路出,输出电流可以做到3A/2A/2A;如有需求请联系我：021-54262182 EXT 114(Eric) QQ：1187337351
上传时间： 2013-11-24
上传用户：fairy0212
Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configured TimerBlox function.DC1562A comes in twelve timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.
上传时间： 2013-10-18
上传用户：如果你也听说
HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C
标签： C8051F020
上传时间： 2013-10-12
上传用户：lalalal
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上传时间： 2013-11-13
上传用户：fredguo
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
PCB设计问题集锦 问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。 答：可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：这是有关制造方面的一个检查，您没有相关设定，所以可以不检查。 问： 怎样导出jop文件？答：应该是JOB文件吧？低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件，方法如下STEP：FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件，再保存为JOB文件。 问： 怎样导入reu文件？答：在ECO与Design 工具盒中都可以进行，分别打开ECO与Design 工具盒，点击右边第2个图标就可以。 问： 为什么我在pad stacks中再设一个via:1(如附件）和默认的standardvi(如附件）在布线时V选择1，怎么布线时按add via不能添加进去这是怎么回事，因为有时要使用两种不同的过孔。答：PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件，如电源类只能用Standard VIA等等，这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问：为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答：首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问：我用ctrl+c复制线时怎设置原点进行复制，ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答： 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问：用(图4)进行修改线时拉起时怎总是往左边拉起(图5)，不知有什么办法可以轻易想拉起左就左，右就右。答： 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问： 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起，而你教程里都会好好的(图8)答：这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问： 尊敬的老师:您好！这个图已经画好了，但我只对（如图1）一种的完全间距进行检查，怎么错误就那么多，不知怎么改进。请老师指点。这个图在附件中请老师帮看一下，如果还有什么问题请指出来，本人在改进。谢！！！！！答：请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问： U101元件已建好，但元件框的拐角处不知是否正确，请帮忙CHECK 答：元件框等可以通过修改编辑来完成。问： U102和U103元件没建完全，在自动建元件参数中有几个不明白：如：SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值，还有这两个元件SILK怎么自动设置，以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答：Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间： 2014-01-03
上传用户：Divine
TIMER.ASM ********* [ milindhp@tifrvax.tifr.res.in ] Set Processor configuration word as = 0000 0000 1010 b. a] -MCLR tied to VDD (internally). b] Code protection off. c] WDT disabled. d] Internal RC oscillator [4 MHZ].
标签： configuration Processor milindhp tifrvax
上传时间： 2015-05-24
上传用户：wqxstar
Use the fast Fourier transform function fft to analyse following signal. Plot the original signal, and the magnitude of its spectrum linearly and logarithmically. Apply Hamming window to reduce the leakage. . The hamming window can be coded in Matlab as for n=1:N hamming(n)=0.54+0.46*cos((2*n-N+1)*pi/N); end; where N is the data length in the FFT.
标签： matlab fft
上传时间： 2015-11-23
上传用户：石灰岩123
Use fft to analyse signal by plotting the original signal and its spectrum.
标签： matlab fft
上传时间： 2015-11-23
上传用户：石灰岩123
信息隐藏软件Outguess的源码 Outguess主要用于JPEg图象的steganography，本软件来自Outguess的作者Provos，欢迎大家下载研究-Information Hiding Outguess source software is mainly used Outguess JPEG image steganography, this software from Outguess author of Provos, welcomed everyone to download research
标签： outguess
上传时间： 2017-03-07
上传用户：Liquor
