用51模拟的TFT RGB接口驱动程序(HS,VS,DE,PCLK时序)
上传时间： 2013-12-24
上传用户：hxy200501
The CC1000 RF transceiver is very easy to interface with a microcontroller. The chip is configured using a three-wire bus, comprising of PCLK, PDATA and PALE signals.
标签： microcontroller transceiver configured The
上传时间： 2014-01-04
上传用户：c12228
电子秒表要实现的功能：用键盘中断来控制整个程序，按一下回车键启动电子秒表，再按一下暂停，按一下ESC键清零，用七段数码管显示时间。整个程序涉及到8255、8253与8259三个芯片。8253的OUT2，CLK2分别连接8259的IRQ7与PCLK，8253的GATE2连接正5伏电压，采用计数器2每隔0.01秒产生一次中断并且计数，写入以偏移地址4000H开始的4个内存单元，然后利用8255将内存单元的数据输出到七段数码管
上传时间： 2014-01-16
上传用户：ukuk
基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .PCLK (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
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