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PCI-Labcard

  • 基于PCI总线的ARINC429接口卡设计

    利用PCI专用接口芯片PCI9052和DEI1016 429总线收发芯片设计了ARINC429接口卡,采用DSP作为主控CPU完成数据自动处理,用双口RAM完成DSP与PCI总线数据交换。实验表明:所设计的接口卡传输效率高,可靠性好,开发简单。

    标签: ARINC PCI 429 总线

    上传时间: 2014-12-30

    上传用户:love1314

  • PCI桥接IP Core的VeriIog HDL实现

    PCI总线是目前最为流行的一种局部性总线 通过对PCI总线一些典型功能的分析以及时序的阐述,利用VetilogHDL设计了一个将非PCI功能设备转接到PC1总线上的IP Core 同时,通过在ModeISim SE PLUS 6.0 上运行测试程序模块,得到了理想的仿真数据波形,从软件上证明了功能的实现。

    标签: VeriIog Core PCI HDL

    上传时间: 2014-12-30

    上传用户:himbly

  • PCI总线的应用

    The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.

    标签: PCI 总线

    上传时间: 2013-11-01

    上传用户:KSLYZ

  • PCI总线规范及其接口

    作为一种独立于处理器的局部总线,PCI非常适用于网络适配器、硬盘驱动器、全动态视频卡、图形卡及各类高速外设。据称,目前有90%的Pentium处理器采用PCI做为系统总线。

    标签: PCI 总线规范 接口

    上传时间: 2013-11-07

    上传用户:liaocs77

  • 基于Virtex5的PCI接口电路

    PCI Express是由Intel,Dell,Compaq,IBM,Microsoft等PCI SIG联合成立的Arapahoe Work Group共同草拟并推举成取代PCI总线标准的下一代标准。PCI Express利用串行的连接特点能轻松将数据传输速度提到一个很高的频率,达到远远超出PCI总线的传输速率。一个PCI Express连接可以被配置成x1,x2,x4,x8,x12,x16和x32的数据带宽。x1的通道能实现单向312.5 MB/s(2.5 Gb/s)的传输速率。Xilinx公司的Virtex5系列FPGA芯片内嵌PCI-ExpressEndpoint Block硬核,为实现单片可配置PCI-Express总线解决方案提供了可能。  本文在研究PCI-Express接口协议和PCI-Express Endpoint Block硬核的基础上,使用Virtex5LXT50 FPGA芯片设计PCI Express接口硬件电路,实现PCI-Express数据传输

    标签: Virtex5 PCI 接口电路

    上传时间: 2013-12-27

    上传用户:wtrl

  • XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

      The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.

    标签: PCI-X XAPP DIMM 708

    上传时间: 2013-11-24

    上传用户:18707733937

  • PCI-PCI桥在线读写EEPROM的技巧

      PCI-PCI 桥启动时,一般需要从EEPROM 预读取配置数据。更改EEPROM中的数据一般需要专用的烧结器,这给调试过程带来不便。尤其是采用表贴封装的EEPROM。本文以Intel 公司的Dec21554PCI-PCI 桥为例,介绍一种在线读写EEPROM 的方法。EEPROM选用的是ATMEL 公司生产的AT93LC66,4Kbit,按512×8bit 组织。

    标签: PCI-PCI EEPROM 在线读写

    上传时间: 2013-11-08

    上传用户:trepb001

  • pci e PCB设计规范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    标签: pci PCB 设计规范

    上传时间: 2014-01-24

    上传用户:s363994250

  • PCI-E8622数据采集卡的功能介绍

    PCI-E是一种高速传输总线形式。

    标签: PCI-E 8622 数据采集卡

    上传时间: 2013-12-18

    上传用户:宋桃子

  • PCI-1734快速安装使用手册

    PCI-1734快速安装使用手册PCI-1734快速安装使用手册PCI-1734快速安装使用手册PCI-1734快速安装使用手册PCI-1734快速安装使用手册PCI-1734快速安装使用手册PCI-1734快速安装使用手册

    标签: 1734 PCI 安装使用

    上传时间: 2013-10-22

    上传用户:ssz1990