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OPTIONS-linker-stack

  • DN492-双单片降压集成温度监控模块

      Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.

    标签: 492 DN 降压 温度监控

    上传时间: 2014-01-03

    上传用户:Huge_Brother

  • Cadence PCB 设计与制板

    §1、安装:    SPB15.2 CD1~3,安装1、2,第3为库,不安装    License安装:         设置环境变量lm_license_file   D:\Cadence\license.dat         修改license中SERVER yyh ANY 5280为SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)设计原理图   进入Design Entry CIS Studio     设置操作环境\Options\Preferencses:       颜色:colors/Print       格子:Grid Display       杂项:Miscellaneous       .........常取默认值

    标签: Cadence PCB

    上传时间: 2013-11-13

    上传用户:wangchong

  • 西门子软件汇总

    西门子PLC S7-200编程软件最新版本(2012.3) STEP7 MicroWIN_V4 SP9 完整版, 全面支持Windows7。安装完后,打开软件,初次为英文版,点击tools(左上角自左-右第6个)然后选择最下面的options(自上而下第15个)单击,出现又一个画面,在左边选择第一个选项General,就出现了语言选项,选择最下面的那个(Chinese)也就是中文。然后点击OK按钮,然后一路回车下去,直到软件关闭,再打开时就是中文的啦!

    标签: 西门子 软件

    上传时间: 2013-11-19

    上传用户:mikesering

  • XAPP444 - CPLD配件,技巧和窍门

    Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.

    标签: XAPP CPLD 444 配件

    上传时间: 2014-01-11

    上传用户:a471778

  • XAPP953-二维列序滤波器的实现

      This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.

    标签: XAPP 953 二维 滤波器

    上传时间: 2013-12-14

    上传用户:逗逗666

  • XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

    XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems

    标签: XAPP FPGA Bank 520

    上传时间: 2013-11-06

    上传用户:wentianyou

  • PowerPCB培训教程

    欢迎使用 PowerPCB 教程。本教程描述了 PADS-PowerPCB  的绝大部分功能和特点,以及使用的各个过程,这些功能包括: · 基本操作 · 建立元件(Component) · 建立板子边框线(Board outline) · 输入网表(Netlist) · 设置设计规则(Design Rule) · 元件(Part)的布局(Placement) · 手工和交互的布线 · SPECCTRA全自动布线器(Route Engine) · 覆铜(Copper Pour) · 建立分隔/混合平面层(Split/mixed Plane) · Microsoft的目标连接与嵌入(OLE)(Object Linking Embedding) · 可选择的装配选件(Assembly options) · 设计规则检查(Design Rule Check) · 反向标注(Back Annotation) · 绘图输出(Plot Output)      使用本教程后,你可以学到印制电路板设计和制造的许多基本知识。

    标签: PowerPCB 培训教程

    上传时间: 2013-10-08

    上传用户:x18010875091

  • Allegro SPB V15.2 版新增功能

    15.2 已經加入了有關貫孔及銲點的Z軸延遲計算功能. 先開啟 Setup - Constraints - Electrical constraint sets  下的 DRC 選項.  點選 Electrical Constraints dialog box 下 Options 頁面 勾選 Z-Axis delay栏. 

    标签: Allegro 15.2 SPB

    上传时间: 2013-11-12

    上传用户:Late_Li

  • Cadence PCB 设计与制板

    §1、安装:    SPB15.2 CD1~3,安装1、2,第3为库,不安装    License安装:         设置环境变量lm_license_file   D:\Cadence\license.dat         修改license中SERVER yyh ANY 5280为SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)设计原理图   进入Design Entry CIS Studio     设置操作环境\Options\Preferencses:       颜色:colors/Print       格子:Grid Display       杂项:Miscellaneous       .........常取默认值

    标签: Cadence PCB

    上传时间: 2014-01-25

    上传用户:wangcehnglin

  • Debug.x:封装SEH 作用:在程序发生未处理的异常时

    Debug.x:封装SEH 作用:在程序发生未处理的异常时,利用SEH获得异常时刻的信息,并将信息显示或存储到文件。 相关:pe文件操作 Stack操作

    标签: Debug SEH 封装 发生

    上传时间: 2015-01-23

    上传用户:lili123