一、变压器Np、Ns、Lp的计算二、如果要计算气隙长度Lg三、开关管Vce、Ic的计算（非连续）五.输出整流二极管Id、Vd的计算Flyback输出滤波电容设计流过输出电容C的纹波电流Ic=I2- Io 其中：I2为次级线圈电流 Ic的有效值可由下式计算：Icrms=[Ton/3T(I2p^2-I2pIo+Io^2 )+(Toff/T)* Io^2]^1/2 其中I2p=2io/(1- δmax) 此为输入电压最低、输出功率最大时状态。
上传时间： 2013-11-22
上传用户：aesuser
QSP-12是一款性/价比极高的直接使用USB通讯协议而开发的三星单片机专用编程器。不同于传统采用USB转RS232的编程器，直接使用USB通讯协议的QSP-12更快更可靠！配合精心优化设计的PC客户端编程（烧录）软件，实现了业界最高的编程性能。自动烧录S3F9454（包含擦除/编程/校验/写Smart option/Read protect/LDC protect/Hard Lock）只须0.7秒，代码越小，烧录越快；代码越大，优势越明显！ 编程器采用小巧而坚实的烤漆铁质外壳设计，具有极高的耐用性和抗电磁干扰能力，配备防止反插的RJ-11专业在线编程接口，确保您在使用过程中没机会出错。QSP-12快速可靠的编程（烧录）能力，无论是您在产品开发、量产，还是在产品的现场升级阶段，它都能给您带来前所未有高效、可靠的编程体验！在现今人力成本日益高涨的时代，为您赢得更多优势！ QSP-12特点： 直接使用USB通讯，更快、更可靠 无需用户设定编程电压，更安全、易用 业界最高的编程性能，节省人力成本 支持脱机烧录 支持在线编程（ISP） 外形小巧，方便产品现场升级 坚实的烤漆铁质外壳，更美观耐用、抗电磁干扰能力强 低功耗（<0.5W），绿色环保
上传时间： 2013-11-19
上传用户：uuuuuuu
winCE msdn讲座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上传时间： 2013-10-31
上传用户：jrsoft
针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上传时间： 2013-11-06
上传用户：liu123
文中详细地介绍了正交投影子空间跟踪算法（OPAST），它是一种基于最优化问题的方法，保证了每次迭代时权向量的正交性，并具有和PAST算法一样的线性复杂度，以及与自然幂法（NP）一样的全局收敛性。然而将其应用于盲多用户检测时，在迭代一定次数后，会出现误码率突然增大现象，这就导致了算法性能的下降，为了解决这一问题，文中提出一种方法，并通过仿真结果，证明它是行之有效的。
上传时间： 2014-11-11
上传用户：xaijhqx
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV set, the stereo, the VCR, and the satellite receiver.
上传时间： 2013-11-13
上传用户：顶得柱
针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上传时间： 2013-11-19
上传用户：neu_liyan
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后，可应用于实际的数字钟显示中。 关键词：Verilog HDL；硬件描述语言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上传时间： 2013-11-10
上传用户：hz07104032
tty驱动 * This driver shows how to create a minimal tty driver. It does not rely on * any backing hardware, but creates a timer that emulates data being received * from some kind of hardware.
标签： driver tty backing minimal
上传时间： 2013-12-04
上传用户：金宜
This companion disc contains the source code for the sample programs presented in INSIDE VISUAL C++ 5.0, as well as pre- compiled copies of the programs. To copy all of the sample code onto your hard disk, run the SETUP.EXE program and follow the instructions that appear on the screen. The sample code requires about 10 MB of hard disk space.
标签： companion the presented contains
上传时间： 2015-05-09
上传用户：mhp0114
