NC-vhdl

USB接口控制器参考设计,xilinx提供VHDL代码 us

USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

标签： xilinx VHDL USB us

上传时间： 2013-10-12

上传用户：windgate
ref sdr sdram vhdl代码

ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

标签： sdram vhdl ref sdr

上传时间： 2013-11-13

上传用户：takako_yang
UART 4 UART参考设计，Xilinx提供VHDL代码

UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.

标签： UART Xilinx VHDL 参考设计

上传时间： 2013-11-07

上传用户：jasson5678
各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:

标签： VHDL 计数器源代码

上传时间： 2013-10-16

上传用户：bjgaofei
各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;

标签： VHDL 计数器源代码

上传时间： 2014-11-30

上传用户：半熟1994
VHDL实用教程(潘松)

VHDL实用教程

标签： VHDL 实用教程

上传时间： 2014-01-04

上传用户：d815185728
8.2+LED控制VHDL程序与仿真

8.2+LED控制VHDL程序与仿真

标签： VHDL 8.2 LED 控制

上传时间： 2013-11-03

上传用户：我们的船长
NAND FLASH 读写控制以及ECC的VHDL源程序

NAND FLASH 读写控制以及ECC的VHDL源程序

标签： FLASH NAND VHDL ECC

上传时间： 2013-10-13

上传用户：003030
VHDL教程讲义

VHDL

标签： VHDL 教程讲义

上传时间： 2013-11-12

上传用户：mqien
FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的，，，，，

标签： FPGA VHDL ARM EPI

上传时间： 2013-10-31

上传用户：chaisz