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MULTIPlier

  • Wallace Tree MULTIPlier in VHDL for 4bit operation fully using structural language

    Wallace Tree MULTIPlier in VHDL for 4bit operation fully using structural language

    标签: MULTIPlier structural operation language

    上传时间: 2014-01-04

    上传用户:hfmm633

  • MULTIPlier BCD - vhdl

    MULTIPlier BCD - vhdl

    标签: MULTIPlier vhdl BCD

    上传时间: 2013-12-27

    上传用户:dongbaobao

  • complement of MULTIPlier

    complement of MULTIPlier

    标签: complement MULTIPlier of

    上传时间: 2013-12-22

    上传用户:helmos

  • 6x6 bit digital MULTIPlier

    6x6 bit digital MULTIPlier

    标签: MULTIPlier digital 6x6 bit

    上传时间: 2014-01-05

    上传用户:bruce

  • Radix 4 Booth MULTIPlier

    Radix 4 Booth MULTIPlier

    标签: MULTIPlier Radix Booth

    上传时间: 2017-09-19

    上传用户:zhuimenghuadie

  • A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth MULTIPlier

    A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth MULTIPlier

    标签: Counterflow-Pipelined Asynchronous MULTIPlier Scalable

    上传时间: 2014-01-04

    上传用户:jjj0202

  • 基于开关电容技术的锁定放大器设计

    锁定放大是微弱信号检测的重要手段。基于相关检测理论,利用开关电容的开关实现锁定放大器中乘法器的功能,提出开关电容和积分器相结合以实现相关检测的方法,并设计出一种锁定放大器。该锁定放大器将微弱信号转化为与之相关的方波,通过后续电路得到正比于被测信号的直流电平,为后续采集处理提供方便。测量数据表明锁定放大器前级可将10-6 A的电流转换为10-1 V的电压,后级通过带通滤波器级联可将信号放大1×105倍。该方法在降低噪声的同时,可对微弱信号进行放大,线性度较高、稳定性较好。 Abstract:  Lock-in Amplifying(LIA)is one of important means for weak signal detection. Based on cross-correlation detection theory, switch in the swithched capacitor was used as MULTIPlier of LIA, and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave, then DC proportional to measured signal was obtained through follow-up conditioning circuit, providing convenience for signal acquisition and processing. The measured data shows that the electric current(10-6 A) can be changed into voltage(10-1 V) by LIA, and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.

    标签: 开关电容 锁定放大器

    上传时间: 2013-11-29

    上传用户:黑漆漆

  • AD9859芯片资料

    FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK MULTIPlier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization

    标签: 9859 AD 芯片资料

    上传时间: 2014-12-04

    上传用户:axin881314

  • 扩频通信芯片STEL-2000A的FPGA实现

    针对传统集成电路(ASIC)功能固定、升级困难等缺点,利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块,在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波,给出了DQPSK解调的原理和实现方法,推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序,在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract:  To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core MULTIPlier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.

    标签: STEL 2000 FPGA 扩频通信

    上传时间: 2013-11-06

    上传用户:liu123

  • 扩频通信芯片STEL-2000A的FPGA实现

    针对传统集成电路(ASIC)功能固定、升级困难等缺点,利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块,在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波,给出了DQPSK解调的原理和实现方法,推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序,在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract:  To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core MULTIPlier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.

    标签: STEL 2000 FPGA 扩频通信

    上传时间: 2013-11-19

    上传用户:neu_liyan