The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
AVR高速嵌入式单片机原理与应用(修订版)详细介绍ATMEL公司开发的AVR高速嵌入式单片机的结构；讲述AVR单片机的开发工具和集成开发环境（IDE）,包括Studio调试工具、AVR单片机汇编器和单片机串行下载编程；学习指令系统时,每条指令均有实例,边学习边调试,使学习者看得见指令流向及操作结果,真正理解每条指令的功能及使用注意事项；介绍AVR系列多种单片机功能特点、实用程序设计及应用实例；作为提高篇,讲述简单易学、适用AVR单片机的高级语言BASCOMAVR及ICC AVR C编译器。 AVR高速嵌入式单片机原理与应用(修订版) 目录 第一章ATMEL单片机简介1.1ATMEL公司产品的特点11.2AT90系列单片机简介21.3AT91M系列单片机简介2第二章AVR单片机系统结构2.1AVR单片机总体结构42.2AVR单片机中央处理器CPU62.2.1结构概述72.2.2通用寄存器堆92.2.3X、Y、Z寄存器92.2.4ALU运算逻辑单元92.3AVR单片机存储器组织102.3.1可下载的Flash程序存储器102.3.2内部和外部的SRAM数据存储器102.3.3EEPROM数据存储器112.3.4存储器访问和指令执行时序112.3.5I/O存储器132.4AVR单片机系统复位162.4.1复位源172.4.2加电复位182.4.3外部复位192.4.4看门狗复位192.5AVR单片机中断系统202.5.1中断处理202.5.2外部中断232.5.3中断应答时间232.5.4MCU控制寄存器 MCUCR232.6AVR单片机的省电方式242.6.1休眠状态242.6.2空闲模式242.6.3掉电模式252.7AVR单片机定时器／计数器252.7.1定时器／计数器预定比例器252.7.28位定时器／计数器0252.7.316位定时器／计数器1272.7.4看门狗定时器332.8AVR单片机EEPROM读／写访问342.9AVR单片机串行接口352.9.1同步串行接口 SPI352.9.2通用串行接口 UART402.10AVR单片机模拟比较器452.10.1模拟比较器452.10.2模拟比较器控制和状态寄存器ACSR462．11AVR单片机I/O端口472.11.1端口A472.11.2端口 B482.11.3端口 C542.11.4端口 D552.12AVR单片机存储器编程612.12.1编程存储器锁定位612.12.2熔断位612.12.3芯片代码612.12.4编程 Flash和 EEPROM612.12.5并行编程622.12．6串行下载662.12.7可编程特性67第三章AVR单片机开发工具3.1AVR实时在线仿真器ICE200693.2JTAG ICE仿真器693.3AVR嵌入式单片机开发下载实验器SL?AVR703.4AVR集成开发环境(IDE)753.4.1AVR Assembler编译器753.4.2AVR Studio773.4.3AVR Prog783.5SL?AVR系列组态开发实验系统793.6SL?AVR*.ASM源文件说明81第四章AVR单片机指令系统4.1指令格式844.1.1汇编指令844.1.2汇编器伪指令844.1.3表达式874.2寻址方式894.3数据操作和指令类型924.3.1数据操作924.3.2指令类型924.3.3指令集名词924.4算术和逻辑指令934.4.1加法指令934.4.2减法指令974.4.3乘法指令1014.4.4取反码指令1014.4.5取补指令1024.4.6比较指令1034.4.7逻辑与指令1054.4.8逻辑或指令1074.4.9逻辑异或指令1104.5转移指令1114.5.1无条件转移指令1114.5.2条件转移指令1144.6数据传送指令1354.6.1直接数据传送指令1354.6.2间接数据传送指令1374.6.3从程序存储器直接取数据指令1444.6.4I／O口数据传送指令1454.6.5堆栈操作指令1464.7位指令和位测试指令1474.7.1带进位逻辑操作指令1474.7.2位变量传送指令1514.7.3位变量修改指令1524.7.4其它指令1614.8新增指令（新器件）1624.8.1EICALL-- 延长间接调用子程序1624.8.2EIJMP--扩展间接跳转1634.8.3ELPM--扩展装载程序存储器1644.8.4ESPM--扩展存储程序存储器1644.8.5FMUL--小数乘法1664.8.6FMULS--有符号数乘法1664.8.7FMULSU--有符号小数和无符号小数乘法1674.8.8MOVW--拷贝寄存器字1684.8.9MULS--有符号数乘法1694.8.10MULSU--有符号数与无符号数乘法1694.8.11SPM--存储程序存储器170 第五章AVR单片机AT90系列5.1AT90S12001725.1.1特点1725.1.2描述1735.1.3引脚配置1745.1.4结构纵览1755.2AT90S23131835.2.1特点1835.2.2描述1845.2.3引脚配置1855.3ATmega8/8L1855.3.1特点1865.3.2描述1875.3.3引脚配置1895.3.4开发实验工具1905.4AT90S2333/44331915.4.1特点1915.4.2描述1925.4.3引脚配置1945.5AT90S4414/85151955.5.1特点1955.5.2AT90S4414和AT90S8515的比较1965.5.3引脚配置1965.6AT90S4434/85351975.6.1特点1975.6.2描述1985.6.3AT90S4434和AT90S8535的比较1985.6.4引脚配置2005.6.5AVR RISC结构2015.6.6定时器/计数器2125.6.7看门狗定时器 2175.6.8EEPROM读/写2175.6.9串行外设接口SPI2175.6.10通用串行接口UART2175.6.11模拟比较器 2175.6.12模数转换器2185.6.13I/O端口2235.7ATmega83/1632285.7.1特点2285.7.2描述2295.7.3ATmega83与ATmega163的比较2315.7.4引脚配置2315.8ATtiny10/11/122325.8.1特点2325.8.2描述2335.8.3引脚配置2355.9ATtiny15/L2375.9.1特点2375.9.2描述2375.9.3引脚配置2395 .10ATmega128/128L2395.10.1特点2405.10.2描述2415.10.3引脚配置2435.10.4开发实验工具2455.11ATmega1612465.11.1特点2465.11.2描述2475.11.3引脚配置2475.12AVR单片机替代MCS51单片机249第六章实用程序设计6．1程序设计方法2506.1.1程序设计步骤2506．1．2程序设计技术2506.2应用程序举例2516.2.1内部寄存器和位定义文件2516.2.2访问内部 EEPROM2546.2.3数据块传送2546.2.4乘法和除法运算应用一2556.2.5乘法和除法运算应用二2556.2.616位运算2556.2.7BCD运算2556.2.8冒泡分类算法2556.2.9设置和使用模拟比较器2556.2.10半双工中断方式UART应用一2556.2.11半双工中断方式UART应用二2566.2.128位精度A／D转换器2566.2.13装载程序存储器2566.2.14安装和使用相同模拟比较器2566.2.15CRC程序存储的检查2566.2.164×4键区休眠触发方式2576.2.17多工法驱动LED和4×4键区扫描2576.2.18I2C总线2576.2.19I2C工作2586.2.20SPI软件2586.2.21验证SLAVR实验器及AT90S1200的口功能12596.2.22验证SLAVR实验器及AT90S1200的口功能22596.2.23验证SLAVR实验器及具有DIP40封装的口功能第七章AVR单片机的应用7.1通用延时子程序2607.2简单I/O口输出实验2667.2.1SLAVR721.ASM 2667.2.2SLAVR722.ASM2677.2.3SLAVR723.ASM2687.2.4SLAVR724.ASM2707.2.5SLAVR725.ASM2717.2.6SLAVR726.ASM2727.2.7SLAVR727.ASM2737.3综合程序2747.3.1LED/LCD/键盘扫描综合程序2747.3.2LED键盘扫描综合程序2757.3.3在LED上实现字符8的循环移位显示程序2757.3.4电脑放音机2777.3.5键盘扫描程序2857.3.6十进制计数显示2867.3.7廉价的A/D转换器2897.3.8高精度廉价的A/D转换器2947.3.9星星灯2977.3.10按钮猜数程序2987.3.11汉字的输入3047.4复杂实用程序3067.4.110位A/D转换3067.4.2步进电机控制程序3097.4.3测脉冲宽度3127.4.4LCD显示8字循环3187.4.5LED电脑时钟3247.4.6测频率3307.4.7测转速3327.4.8AT90S8535的A/D转换334第八章BASCOMAVR的应用8.1基于高级语言BASCOMAVR的单片机开发平台3408.2BASCOMAVR软件平台的安装与使用3418.3AVR I/O口的应用3458.3.1LED发光二极管的控制3458.3.2简易手控广告灯3468.3.3简易电脑音乐放音机3478.4LCD显示器3498.4.1标准LCD显示器的应用3498.4.2简单游戏机--按钮猜数3518.5串口通信UART3528.5.1AVR系统与PC的简易通信3538.5.2PC控制的简易广告灯3548.6单总线接口和温度计3568.7I2C总线接口和简易IC卡读写器359第九章ICC AVR C编译器的使用9.1ICC AVR的概述3659.1.1介绍ImageCraft的ICC AVR3659.1.2ICC AVR中的文件类型及其扩展名3659.1.3附注和扩充3669.2ImageCraft的ICC AVR编译器安装3679.2.1安装SETUP.EXE程序3679.2.2对安装完成的软件进行注册3679.3ICC AVR导游3689.3.1起步3689.3.2C程序的剖析3699.4ICC AVR的IDE环境3709.4.1编译一个单独的文件3709.4.2创建一个新的工程3709.4.3工程管理3719.4.4编辑窗口3719.4.5应用构筑向导3719.4.6状态窗口3719.4.7终端仿真3719.5C库函数与启动文件3729.5.1启动文件3729.5.2常用库函数3729.5.3字符类型库3739.5.4浮点运算库3749.5.5标准输入/输出库3759.5.6标准库和内存分配函数3769.5.7字符串函数3779.5.8变量参数函数3799.5.9堆栈检查函数3799.6AVR硬件访问的编程3809.6.1访问AVR的底层硬件3809.6.2位操作3809.6.3程序存储器和常量数据3819.6.4字符串3829.6.5堆栈3839.6.6在线汇编3839.6.7I/O寄存器3849.6.8绝对内存地址3849.6.9C任务3859.6.10中断操作3869.6.11访问UART3879.6.12访问EEPROM3879.6.13访问SPI3889.6.14相对转移/调用的地址范围3889.6.15C的运行结构3889.6.16汇编界面和调用规则3899.6.17函数返回非整型值3909.6.18程序和数据区的使用3909.6.19编程区域3919.6.20调试3919.7应用举例*3929.7.1读/写口3929.7.2延时函数3929.7.3读/写EEPROM3929.7.4AVR的PB口变速移位3939.7.5音符声程序3939.7.68字循环移位显示程序3949.7.7锯齿波程序3959.7.8正三角波程序3969.7.9梯形波程序396附录1AT89系列单片机简介398附录2AT94K系列现场可编程系统标准集成电路401附录3指令集综合404附录4AVR单片机选型表408参 考 文 献412
上传时间： 2013-11-08
上传用户：xcy122677
基于单片机的汽车多功能报警系统设计The Design of Automobile Multi-function AlarmingBased on Single Chip Computer刘法治赵明富宁睡达(河 南 科 技 学 院 ，新 乡 453 00 3)摘要介绍了一种基于单片机控制的汽车多功能报警系统，它能对汽车的润滑系统油压、制动系统气压、冷却系统温度、轮胎欠压及防盗进行自动检测，并在发现异常情况时，发出声光报警。阐述了该报警系统的硬件组成及软件设计方法。关键词单片机传感器数模转换报警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly场thesystem. Audio and visual alarms wil be provided under abnormal conditions厂The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽车多功能报苦器硬件系统设计根据 系 统 实际需要和产品性价比，选用ATMEL公司新生产的采用CMOs工艺的低功耗、高性能8位单片机AT89S52作为系统的控制器。AT89S52的片内有8k Bytes LSP Flash闪烁存储器，可进行100(〕次写、擦除操作;256Bytes内部数据存储器(RAM);3 2 根可编程输N输出线;2个可编程全双工串行通道;看门狗(WTD)电路等。系统由传感器、单片机、模数转换器、无线信号发射电路、指示灯驱动电路、声光报警驱动电KD一9563，发出三声二闪光。并触发一个高电平，驱动无线信号发射电路。
上传时间： 2013-11-09
上传用户：gxmm
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
为提升虚拟仪器传输速率与实时性能，扩展监测范围，在VC的软件平台上设计了一种全功能虚拟示波器。与传统虚拟示波器相比，该系统采用嵌入式系统完成信号采集，采用工业以太网为传输介质，通过线性插值算法和多线程编程思想，实现波形显示、参数计算、频谱分析以及波形存储及回放功能。实验结果表明，该虚拟示波器可以实现20 kHz采样频率下的波形精确显示，达到预期的各项指标。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
上传时间： 2013-11-25
上传用户：wbwyl
同步技术是跳频通信系统的关键技术之一，尤其是在快速跳频通信系统中，常规跳频通信通过同步字头携带相关码的方法来实现同步，但对于快跳频来说，由于是一跳或者多跳传输一个调制符号，难以携带相关码。对此引入双跳频图案方法，提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息，克服了快速跳频难以携带相关码的困难。分析了同步性能，仿真结果表明该方案同步时间短、虚警概率低、捕获概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上传时间： 2013-11-23
上传用户：mpquest
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上传时间： 2014-01-17
上传用户：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
上传时间： 2013-10-30
上传用户：ysjing
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上传时间： 2013-11-10
上传用户：yy_cn
