core java2 v1 7th edition
上传时间： 2013-12-29
上传用户：aig85
Development of LDPC Encoder/Decoder core
标签： Development Decoder Encoder LDPC
上传时间： 2017-06-24
上传用户：jjj0202
在ADS编译环境以及keil-ARM这两种编译环境下通用的arm-core头文件，并用金鹏串行12864进行验证，用此arm-core开发程序可以不受编译器头文件缺少的限制
标签： keil-ARM arm-core ADS 编译环境
上传时间： 2014-01-14
上传用户：hustfanenze
New to Python? This is the developer s guide to Python development! q Learn the core features of Python as well as advanced topics such as regular expressions, multithreaded programming, Web/Internet and network development, GUI development with Tk(inter) and more
标签： Python development developer the
上传时间： 2013-12-06
上传用户：lizhen9880
OFDM与MC-CDMA技术的比较与MC-CDMA技术的一些相关介绍
上传时间： 2017-06-25
上传用户：chenjjer
Implements a 16550/16750 UART core
标签： Implements 16550 16750 UART
上传时间： 2017-06-25
上传用户：咔乐坞
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
标签： Consecutive Description AES Features
上传时间： 2017-06-25
上传用户：talenthn
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
标签： configurable controller universal adaptive
上传时间： 2017-06-25
上传用户：皇族传媒
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
标签： Tensilica OpenCores interface the
上传时间： 2013-12-21
上传用户：gonuiln
有关MC-CDMA的一些相关技术和相关处理方法
上传时间： 2014-01-13
上传用户：亚亚娟娟123
