16位A/D转换程序，使用MAX+PLUS2做的，用状态机做的，但不够完善，望大家见谅
上传时间： 2016-07-23
上传用户：赵云兴
The task of clustering Web sessions is to group Web sessions based on similarity and consists of maximizing the intra- group similarity while minimizing the inter-group similarity． The first and foremost question needed to be considered in clustering W b sessions is how to measure the similarity between Web sessions．However．there are many shortcomings in traditiona1 measurements．This paper introduces a new method for measuring similarities between Web pages that takes into account not only the URL but also the viewing time of the visited web page．Yhen we give a new method to measure the similarity of Web sessions using sequence alignment and the similarity of W eb page access in detail Experiments have proved that our method is valid and e币cient．
标签： sessions clustering similarity Web
上传时间： 2014-01-11
上传用户：songrui
在LP2900工作平台上，利用MAX+plusII开发软件，设计各个模块编程实现基本模型计算机，其中最主要的是CPU的设计。 独立完成运算器的设计，并下载仿真
上传时间： 2014-12-22
上传用户：15071087253
使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0—99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求
上传时间： 2016-08-29
上传用户：无聊来刷下
中山大学编译原理课程的一个实验，根据OPP(算符优先)做的一个表达式计算器。 内有实验的设计文档。 实验要求支持sin,cos,max,min,power,mod,boolean,?:,等运算。 这个代码可以为学习编译原理的同学参考。
上传时间： 2014-01-27
上传用户：PresidentHuang
用prim算法实验最小生成树 本程序中用到函数adjg( )，此函数作用是通过接受输入的点数和边数，建立无向图。函数prg( )用于计算并输出无向图的邻接矩阵。函数prim( )则用PRIM算法来寻找无向图的最小生成树 定义了两个数组lowcost[max],closest[max]，若顶点k加入U中，则令lowcost[k]=0。 定义二维数组g[ ][ ]来建立无向图的邻接矩阵。
上传时间： 2016-10-07
上传用户：tonyshao
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
标签： Description Behavorial wb_master Filename
上传时间： 2014-07-11
上传用户：zhanditian
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
标签： bus bidirectional primarily designed
上传时间： 2013-12-11
上传用户：jeffery
采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路
上传时间： 2016-11-13
上传用户：zhyiroy
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告
上传时间： 2013-12-09
上传用户：hphh
