AVR single-chip developed by a very low threshold, as long as the computer will be able to study the development of AVR microcontroller. Only a single-chip ISP download beginners line, the editing, debugging of software programs through a direct line into the AVR microcontroller, which can develop AVR Series Single-chip package of a variety of devices. AVR single-chip microcomputer in the industry known as "front-line struggle to seize state power."
标签: single-chip developed threshold the
上传时间: 2017-09-12
上传用户:shinesyh
AVR single-chip developed by a very low threshold, as long as the computer will be able to study the development of AVR microcontroller. Only a single-chip ISP download beginners line, the editing, debugging of software programs through a direct line into the AVR microcontroller, which can develop AVR Series Single-chip package of a variety of devices. AVR single-chip microcomputer in the industry known as "front-line struggle to seize state power."
标签: single-chip developed threshold the
上传时间: 2013-12-09
上传用户:invtnewer
Visual Basic Low Level Disk Acces
上传时间: 2013-12-23
上传用户:王楚楚
The STi7105 uses state of the art process technology to provide an ultra low-cost, fully featured HD AVC decoder IC. It is a highly integrated system-on-chip suitable for STB markets across all networks (cable/satellite/DTT/x- DSL/IP) worldwide
标签: technology low-cost featured process
上传时间: 2013-12-22
上传用户:时代电子小智
Buffer low THD distortion and hi-impendance, Very wide frequency band.
标签: hi-impendance distortion frequency Buffer
上传时间: 2014-08-08
上传用户:dragonhaixm
PXA270 design guide low level primitives
标签: primitives design guide level
上传时间: 2014-06-30
上传用户:yxgi5
Low density parity check matrix
标签: density parity matrix check
上传时间: 2014-01-08
上传用户:yt1993410
本系统采用电动机电枢供电回路串接采样电阻的方式来实现对小型直流有刷电动机的转速测量。该系统主要由二阶低通滤波电路,小信号放大电路、单片机测量显示电路、开关稳压电源电路等组成。同时自制电机测速装置,用高频磁环作为载体,用线圈绕制磁环,利用电磁感应原理检测电机运行时的漏磁,将变化的磁场信号转化为磁环上的感应电流。用信号处理单元电路将微弱电信号转化为脉冲信号,送由单片机检测,从而达到准确测量电机的速度的要求。In this system, the sampling resistance of armature power supply circuit is connected in series to measure the speed of small DC brush motor. The system is mainly composed of second-order low-pass filter circuit, small signal amplifier circuit, single-chip measurement and display circuit, switching regulated power supply circuit and so on. At the same time, the self-made motor speed measuring device uses high frequency magnetic ring as the carrier, coil winding magnetic ring, and electromagnetic induction principle to detect the leakage of magnetic field during the operation of the motor, which converts the changed magnetic field signal into the induced current on the magnetic ring. The weak electric signal is transformed into pulse signal by signal processing unit circuit, which is sent to single chip computer for detection, so as to meet the requirement of accurate measurement of motor speed.
标签: 直流电动机
上传时间: 2022-03-26
上传用户:
现代社会信息量爆炸式增长,由于网络、多媒体等新技术的发展,用户对带宽和速度的需求快速增加。并行传输技术由于时钟抖动和偏移,以及PCB布线的困难,使得传输速率的进一步提升面临设计的极限;而高速串行通信技术凭借其带宽大、抗干扰性强和接口简单等优势,正迅速取代传统的并行技术,成为业界的主流。 本论文针对目前比较流行并且有很大发展潜力的两种高速串行接口电路——高速链路口和Rocket I/O进行研究,并以Xilinx公司最新款的Virtex-5 FPGA为研究平台进行仿真设计。本论文的主要工作是以某低成本相控阵雷达信号处理机为设计平台,在其中的一块信号处理板上,进行了基于LVDS(Low VoltageDifferential Signal)技术的高速LinkPort(链路口)设计和基于CML(Current ModeLogic)技术的Rocket I/O高速串行接口设计。首先在FPGA的软件中进行程序设计和功能、时序的仿真,当仿真验证通过之后,重点是在硬件平台上进行调试。硬件调试验证的方法是将DSP TS201的链路口功能与在FPGA中的模拟高速链路口相连接,进行数据的互相传送,接收和发送的数据相同,证明了高速链路口设计的正确性。并且在硬件调试时对Rocket IO GTP收发器进行回环设计,经过回环之后接收到的数据与发送的数据相同,证明了Rocket I/O高速串行接口设计的正确性。
上传时间: 2013-04-24
上传用户:恋天使569
LDPC(Low Density Parity Check)码是一类可以用非常稀疏的校验矩阵或二分图定义的线性分组纠错码,最初由Gallager发现,故亦称Gallager码.它和著名Turbo码相似,具有逼近香农限的性能,几乎适用于所有信道,因此成为近年来信道编码界研究的热点。 LDPC码的奇偶校验矩阵呈现稀疏性,其译码复杂度与码长成线性关系,克服了分组码在长码长时所面临的巨大译码计算复杂度问题,使长编码分组的应用成为可能。而且由于校验矩阵的稀疏特性,在长的编码分组时,相距很远的信息比特参与统一校验,这使得连续的突发差错对译码的影响不大,编码本身就具有抗突发差错的特性。 本文首先介绍了LDPC码的基本概念和基本原理,其次,具体介绍了LDPC码的构造和各种编码算法及其生成矩阵的产生方法,特别是准循环LDPC码的构造以及RU算法、贪婪算法,并在此基础上采用贪婪算法对RU算法进行了改进。 最后,选用Altera公司的Stratix系列FPGA器件EPls25F67217,实现了码长为504的基于RU算法的LDPC编码器。在设计过程中,为节省资源、提高速度,在向量存储时采用稀疏矩阵技术,在向量相加时采用通过奇校验直接判定结果的方法,在向量乘法中,采用了前向迭代方法,避开了复杂的矩阵求逆运算。结果表明,该编码器只占用约10%的逻辑单元,约5%的存储单元,时钟频率达到120MHz,数据吞吐率达到33Mb/s,功能上也满足编码器的要求。
上传时间: 2013-06-09
上传用户:66wji