The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal Logic against powering up in the wrongstate.
上传时间： 2013-11-20
上传用户：ynzfm
IntroductionAs chip designers pack more functions into ICs,pin counts continue to grow and the space betweenpins keeps shrinking. Pin spacings of 0.5 mm and0.65 mm are not at all uncommon. The power ofthese new ICs is wonderful, to be sure, but trou-bleshooting them can be a chore because connect-ing scopes and Logic analyzers has become muchmore difficult and less dependable.
标签： Agilent Probing Wedge High
上传时间： 2013-10-22
上传用户：蒋清华嗯
Nios 的用户定义接口逻辑实例 有许多人问我使用 Nios 的用户定义接口逻辑怎么用，想了几天决定设计一个实例来说明。该例为一个使用 user to interface Logic 设计的 PWM 实例，其中包括三个文件： plus32.v 是一个为 32bit nios 设计的 pwm 实例。 plus16.v 是一个为 16bit nios 设计的 pwm 实例。 test.s 是一个使用中断调用 pwm 的汇编语言测试程序。以上模块和程序均调试通过，并可稳定工作。这里让大家参考是使大家通过该例来真正理解 user to interface Logic 设计方法，和nios 中通过汇编调用中断的方法，所以超值喔。另外热烈欢迎大家的指导。 注：在设计 Nios 时，将你调用的 user to interface Logic 插件重命名为 plus_0，这样我的 test.s 可不作任何改动，你就可用示波器通过 nios 的 plus 管脚观察到一个要求的输出。
上传时间： 2013-11-15
上传用户：cc1915
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (Logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (Logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上传时间： 2014-11-22
上传用户：xcy122677
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a Logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging sensitive circuitry.
上传时间： 2013-10-24
上传用户：hbsunhui
Designing Boards with Atmel AT89C51, AT89C52, AT89C1051, and AT89C2051 for Writing Flash at In-Circuit Test:Recent improvements in chips andtesters have made it possible for thetester to begin taking over the role traditionallyassigned to the PROM programmer.Instead of having a PROM programmerwrite nonvolatile memoriesbefore assembling the board, the in-circuittester writes them during in-circuittesting operations. Many Teradyne Z18-series testers are now in use loadingcode into nonvolatile memories, microcontrollersand in-circuit programmable Logic devices. The purpose of this note is to explain how the Z18 approaches the writing task for Atmel AT89C series IC’s,so that designers of boards using these chips can get the best results.
标签： Designing Boards Atmel with
上传时间： 2013-11-20
上传用户：lijianyu172
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have Logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上传时间： 2013-10-21
上传用户：xiaozhiqban
一、Rainbow Blaster 的特性Rainbow Blaster全面兼容Altera的USB Blaster下载电缆，通过计算机的USB接口可对Altera的FPGA/CPLD以及配置芯片进行编程、调试等操作。支持的Altera FPGA/CPLD器件如下：l Stratix II、Stratix GX及Stratix系列l Cyclone II及Cyclone系列l APEX II 及APEX 20K系列l ACEX 1Kl Mercuryl FLEX 10K、FLEX 10KE和FLEX 10KA全系列l Excaliburl MAX 3000、MAX 7000和MAX II全系列支持的配置芯片如下：l EPC2, EPC4, EPC8, EPC16, EPC1441l EPCS1, EPCS4, EPCS16,EPCS64支持的目标板IO电压：l 1.5V、1.8V、2.5V、3.3V、5V二、Rainbow Blaster工作需求1.软件需求：l Windows 2000 和XP 操作系统。l 需要安装QuartusII4.0 及以上版本。l Quartus II Programmer (编程或配置操作需要)l Quartus II SignalTap II Logic Analyzer (逻辑分析操作需要)2. 电源需求：l 从USB 电缆的PC 端提供直流5.0V；l 从目标板下载接口提供直流1.5V 至5.0V。三、硬件连接请按如下步骤顺序操作：1. 关掉目标板电源。2. 将USB 电缆一端（大口）接到PC 或笔记本电脑上的USB 接口，另一端（小口）接到Rainbow Blaster。3. 将Rainbow Blaster 的10PIN Female（母头）接头按照方向指示连接到目标
上传时间： 2013-10-15
上传用户：yd19890720
Designing withProgrammable Logicin an Analog WorldProgrammable Logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-Logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable Logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
标签： Solutions Analog Xilinx FPGAs
上传时间： 2013-11-01
上传用户：a67818601
Designing withProgrammable Logicin an Analog WorldProgrammable Logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-Logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable Logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
标签： Solutions Analog Altera FPGAs
上传时间： 2013-11-08
上传用户：虫虫虫虫虫虫
