为解决直流逆变交流的问题，有效地利用能源，让电源输出最大功率，设计了高性能的基于IR2101最大功率跟踪逆变器，并以SPMC75F2413A单片机作为主控制器。高电压、高速功率的MOSFET或IGBT驱动器IR2101采用高度集成的电平转换技术，同时上管采用外部自举电容上电，能够稳定高效地驱动MOS管。该逆变器可以实现DC/AC的转换，最大功率点的跟踪等功能。实际测试结果表明，该逆变器系统具有跟踪能力强，稳定性高，反应灵敏等特点，该逆变器不仅可应用于普通的电源逆变系统，而且可应用于光伏并网发电的逆变系统，具有广泛的市场前景。 Abstract: To solve the problem of DC-AC inverter， and to utilize solar energy more efficiently， the design of maximum power point tracking inverter based on IR2101 was achieved with a high-performance， which can make the system output power maximum. SPMC75F2413A was adopted as main controller. IR2101 is a high voltage， high speed power MOSFET and IGBT driver. It adopted highly integrated voltage level transforming technology， and an external bootstrap capacitor was used， which could drive MOS tube efficiently and stably. Many functions are achieved in the system， such as DC/AC conversion， maximun power point tracking， etc. The actual test result shows that the inverter system has characteristics of strong tracking ability， high stability and reacting quickly. The design can not only be used in ordinary power inverter system， but also be used in photovoltaic power inverter system. The design has certain marketing prospects
上传时间： 2013-11-17
上传用户：lliuhhui
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost.
上传时间： 2013-10-12
上传用户：司令部正军级
为了使音频信号分析仪小巧可靠，成本低廉，设计了以2片MSP430F1611单片机为核心的系统。该系统将音频信号送入八阶巴特沃兹低通滤波器，对信号进行限幅放大、衰减、电平位移、缓冲，并利用一单片机负责对前级处理后的模拟信号进行采样，将采集得到的音频信号进行4 096点基2的FFT计算，并对信号加窗函数提高分辨率，另一单片机负责对信号的分析及控制显示设备。此设计精确的测量了音频信号的功率谱、周期性、失真度指标，达到较高的频率分辨率，并能将测量结果通过红外遥控器显示在液晶屏上。 Abstract: o make the audio signal analyzer cheaper， smaller and more reliable， this system sends the audio signal to the eight-order butterworth filter， and then amplifies， attenuates， buffers it in a limiting range， transfers the voltage level of the signal before utilizing two MSP430F1611 MCU to realize the audio analysis. One is charged for sampling and dealing with the processed audio signal collected by the 4096 point radix-2 FFT calculation and imposes the window function to improve the frequency resolution. The other one controls the display and realizes the spectrum， periodicity， power distortion analysis in high resolution which is displayed in the LCD screen through the infrared remote control.
上传时间： 2013-12-11
上传用户：jasonheung
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上传时间： 2013-11-15
上传用户：zouxinwang
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： High-speed transce 1042 TJA
上传时间： 2014-12-28
上传用户：气温达上千万的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
标签： High-speed transce 1051 TJA
上传时间： 2013-10-17
上传用户：jisujeke
摘要：本水位监测报警器使用5V低压直流电源（也可以用3节5号电池代替）就可以对5~15厘米的水位进行监测，用LED显示和数码管显示水位，并可以对不再此范围内的水位发出报警。主要采用CD4066、74LS86、74LS32、CD4511芯片，再加上数码管、蜂鸣器、发光二极管、电阻这些器件组成一个简单而灵敏的监测报警电路，操作简单，接通电源即可工作。因为大部分电路采用数字电路，所以本水位监测报警器还具有耗能低、准确性高的特点。关键字：译码电路 报警电路 监测电路 Abstract: The water level alarm monitoring the use of 5 V low-voltage DC power (can also use three batteries replaced on the 5th) will be able to 5 to 15 centimeters of water level monitoring, with LED display and digital display of water level, and this can no longer Within the scope of a water level alarm. Mainly CD4066, 74LS86, 74LS32, CD4511 chips, coupled with digital control, buzzer, light-emitting diode, the resistance of these devices composed of a simple and sensitive monitoring alarm circuits. Because the majority of circuits using digital circuitry, so the water level monitored alarm system also has low energy consumption, high accuracy of the characteristics. Keyword: Decoding circuit alarm circuit monitoring circuit
上传时间： 2013-11-05
上传用户：王庆才
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
