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GENERATION

  • 半导体器件物理与设计

    It would not be an exaggeration to say that semiconductor devices have transformed humanlife. From computers to communications to internet and video games these devices and the technologies they have enabled have expanded human experience in a way that is unique in history. Semiconductor devices have exploited materials, physics and imaginative applications to spawn new lifestyles. Of course for the device engineer, in spite of the advances, the challenges of reaching higher frequency, lower power consumption, higher power GENERATION etc.

    标签: 半导体器件 物理

    上传时间: 2013-10-28

    上传用户:songnanhua

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-GENERATION Architecture for Your Next-GENERATION Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process GENERATION ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman

  • 采用TÜV认证的FPGA开发功能安全系统

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power GENERATION, distribution, and transportation. 图Figure 1. Local Safety System

    标签: FPGA 安全系统

    上传时间: 2013-11-14

    上传用户:zoudejile

  • WP312-Xilinx新一代28nm FPGA技术简介

    Xilinx Next GENERATION 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new GENERATION of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

    标签: Xilinx FPGA 312 WP

    上传时间: 2013-12-07

    上传用户:bruce

  • Complete support for EBNF notation; Object-oriented parser design; C++ output; Deterministic bottom-

    Complete support for EBNF notation; Object-oriented parser design; C++ output; Deterministic bottom-up "shift-reduce" parsing; SLR(1), LALR(1) and LR(1) table construction methods; Automatic parse tree creation; Possibility to output parse tree in XML format; Verbose conflict diagnostics; GENERATION of tree traverse procedures

    标签: Object-oriented Deterministic Complete notation

    上传时间: 2014-11-29

    上传用户:kr770906

  • This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is wr

    This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN GENERATION) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.

    标签: simulation baseband channel packet

    上传时间: 2014-11-09

    上传用户:hwl453472107

  • CC386 is a general-purpose 32-bit C compiler. It is not an optimizing compiler but given that the co

    CC386 is a general-purpose 32-bit C compiler. It is not an optimizing compiler but given that the code GENERATION is fairly good. There are two versions one is for MSDOS/DPMI and one is for Win32. The Win32 version has a full-blown IDE capable of editing, building, and debugging windows programs included with it. However at this time debugging support for MSDOS is rudimentary at best and there is no IDE for DOS. the newest version, support windows.

    标签: compiler general-purpose optimizing given

    上传时间: 2015-04-12

    上传用户:gtzj

  • 3GPP文件格式标准

    3GPP文件格式标准,英文版。 3rd GENERATION Partnership Project Technical Specification Group Services and System Aspects Transparent end-to-end packet switched streaming service (PSS) 3GPP file format (3GP) (Release 6)

    标签: 3GPP 文件格式 标准

    上传时间: 2013-12-10

    上传用户:Avoid98

  • GNetWatch is a free open source Java POJO application that enables real-time graphical monitoring an

    GNetWatch is a free open source Java POJO application that enables real-time graphical monitoring and analysis of network performances through SNMP, ICMP and traffic GENERATION modules

    标签: application monitoring GNetWatch graphical

    上传时间: 2013-12-18

    上传用户:aig85

  • his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is w

    his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN GENERATION) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.

    标签: simulation baseband channel packet

    上传时间: 2013-12-23

    上传用户:zhangyigenius