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GENERATE

  • Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

    Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was to GENERATE complex models with a movable camera. We wanted to be able to render complex images that consisted of hundreds to thousands of triangles. We wanted to apply interpolated shading on the objects, so that they appeared more smooth and realisitc, and to have a camera that orbitted around the object, which allowed us to look arond the object with a stationary light source. We chose to do this in hardware, because our initial implementation using running software on the NIOS II processor was too slow. Implementing parallelism in hardware is also easier to do than in software, which allows for more efficiency. We used Professor Land s floating point hardware, which allowed us to do calculations efficiency, which is essential to graphics.

    标签: Implementation Processing Graphics rendered

    上传时间: 2014-11-22

    上传用户:shawvi

  • PCI9052DemoDDK.rar

    本驱动程序对于开发PCI的底层协议驱动很有研究价值,能生成用户需要的sys文件-the driver for the development of the underlying agreement PCI great research value-driven, users can GENERATE the necessary documents sys

    标签: PCI DDK

    上传时间: 2015-02-27

    上传用户:风之音谁懂

  • Writing Analytically ( 6th Edition )

    《分析性写作》,介绍言简意赅: The popular, brief rhetoric that treats writing as thinking, WRITING ANALYTICALLY, Sixth Edition, offers a series of prompts that lead you through the process of analysis and synthesis and help you to GENERATE original and well-developed ideas. The book's overall point is that learning to write well means learning to use writing as a way of thinking well. To that end, the strategies of this book describe thinking skills that employ writing. As you will see, this book treats writing as a tool of thought--a means of undertaking sustained acts of inquiry and reflection.

    标签: Writing Analyticall

    上传时间: 2015-08-22

    上传用户:东大寺的

  • keil单片机编写程序

     1. 安装Keil C51 V8.16版本,即uV3     2. 打开uVision3,点击File---License Management...,打开License Management窗口,复制右上角的CID     3. 打开注册机, 在CID窗口里填上刚刚复制的CID,其它设置不变     4. 点击GENERATE生成许可号,复制许可号     5. 将许可号复制到License Management窗口下部的New License ID Code,点击右侧的Add LIC     6. 若上方的Product显示的是PK51 Prof. Developers Kit即注册成功,Support Period为有效期,一般可以到30年左右,若有效期较短,可多次生成许可号重新注册。

    标签: keil 单片机 注册机

    上传时间: 2016-02-25

    上传用户:woshishabi

  • RVDS2.2破解工具

    RealView Developer Suite v2.2 破解 (2009-12-11)  使用RealView Developer Suite v2.2,传说中的RVDS 2.2,破解也有问题,经过我琢磨。   破解步骤修改如下: 1)用GENERATE产生license file (注意自己的系统时间   最好是真实的当前时间,如果时间比较旧的话,产生的license file 将不能注册。license file 和系统时间、网卡物理地址、硬盘的序列号有关) 2)安装软件 3)license Wizard     选  Install Wizard   ...   选择license file 目录    4)应用补丁注入工具Patch.exe给下边列出的文件注入校验和。文件目录见下边。     从这个论坛下载说明少了4个文件路径,导致的结果就是无法启动调试部分。   关于 no license check  out   以上作完了就加载一个*.axf文件实验吧,看看还有没有no license check  out  ,这时你在看软件注册信息 Enjoy ;-)   Install, apply our patch then GENERATE license file with the keygen.   -------------   the files need to be patched:      %Install Path%\IDEs\CodeWarrior\CodeWarrior\5.6.1\1592\win_32-pentium\bin\Plugins\License\oemlicense.dll   %Install Path%\IDEs\CodeWarrior\RVPlugins\1.0\86\win_32-pentium\oemlicense\oemlicense.dll   %Install Path%\RDI\armsd\1.3.1\66\win_32-pentium\armsd.exe   %Install Path%\RDI\AXD\1.3.1\98\win_32-pentium\axd.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armasm.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armcc.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armcpp.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\armlink.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\fromelf.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\tcc.exe   %Install Path%\RVCT\Programs\2.2\349\win_32-pentium\tcpp.exe   %Install Path%\RVD\Core\1.8\734\win_32-pentium\bin\tvs.exe   %Install Path%\RVD\Core\1.8\734\win_32-pentium\bin\xry100.dll

    标签: RVDS2 破解

    上传时间: 2017-01-18

    上传用户:zbxinu

  • Next Generation Mobile Broadcasting

    Mobile wireless communications are in constant evolution due to the continu- ously increasing requirements and expectations of both users and operators. Mass multimedia* services have been for a long time expected to GENERATE a large amount of data traffic in future wireless networks [1]. Mass multimedia services are, by definition, purposed for many people. In general, it can be distinguished between the distribution of any popular content over a wide area and the distribu- tion of location-dependent information in highly populated areas. Representative examples include the delivery of live video streaming content (like sports compe- titions, concerts, or news) and file download (multimedia clips, digital newspa- pers, or software updates).

    标签: Broadcasting Generation Mobile Next

    上传时间: 2020-05-31

    上传用户:shancjb

  • Signal Processing for Telecommunications

    This paper presents a Hidden Markov Model (HMM)-based speech enhancement method, aiming at reducing non-stationary noise from speech signals. The system is based on the assumption that the speech and the noise are additive and uncorrelated. Cepstral features are used to extract statistical information from both the speech and the noise. A-priori statistical information is collected from long training sequences into ergodic hidden Markov models. Given the ergodic models for the speech and the noise, a compensated speech-noise model is created by means of parallel model combination, using a log-normal approximation. During the compensation, the mean of every mixture in the speech and noise model is stored. The stored means are then used in the enhancement process to create the most likely speech and noise power spectral distributions using the forward algorithm combined with mixture probability. The distributions are used to GENERATE a Wiener filter for every observation. The paper includes a performance evaluation of the speech enhancer for stationary as well as non-stationary noise environment.

    标签: Telecommunications Processing Signal for

    上传时间: 2020-06-01

    上传用户:shancjb

  • 1 Seismic response control using electromagnetic

    This paper presents a new type of electromagnetic damper with rotating inertial mass that has been devel oped to control the vibrations of structures subjected to earthquakes. The electromagnetic inertial mass damper (EIMD) consists of a ball screw that converts axial oscillation of the rod end into rotational motion of the internal flflywheel and an electric generator that is turned by the rotation of the inner rod. The EIMD is able to GENERATE a large inertial force created by the rotating flflywheel and a variable damping force devel oped by the electric generator. Device performance tests of reduced-scale and full-scale EIMDs were under taken to verify the basic characteristics of the damper and the validity of the derived theoretical formulae. Shaking table tests of a three-story structure with EIMDs and earthquake response analyses of a building with EIMDs were conducted to demonstrate the seismic response control performance of the EIMD. The EIMD is able to reduce story drifts as well as accelerations and surpasses conventional types of dampers in reducing acceleration responses.

    标签: electromagnetic response Seismic control using

    上传时间: 2021-11-04

    上传用户:a1293065

  • 基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明

    基于FPGA设计的字符VGA  LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中,再从ROM 中把转换后的数据读取出来显示到 VGA 上,FPGA型号Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。module top( input                       clk, input                       rst_n, //vga output         output                      vga_out_hs, //vga horizontal synchronization          output                      vga_out_vs, //vga vertical synchronization                   output[4:0]                 vga_out_r,  //vga red output[5:0]                 vga_out_g,  //vga green output[4:0]                 vga_out_b   //vga blue );wire                            video_clk;wire                            video_hs;wire                            video_vs;wire                            video_de;wire[7:0]                       video_r;wire[7:0]                       video_g;wire[7:0]                       video_b;wire                            osd_hs;wire                            osd_vs;wire                            osd_de;wire[7:0]                       osd_r;wire[7:0]                       osd_g;wire[7:0]                       osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r  = osd_r[7:3]; //discard low bit dataassign vga_out_g  = osd_g[7:2]; //discard low bit dataassign vga_out_b  = osd_b[7:3]; //discard low bit data//GENERATE video pixel clockvideo_pll video_pll_m0( .inclk0                (clk                        ), .c0                    (video_clk                  ));color_bar color_bar_m0( .clk                   (video_clk                  ), .rst                   (~rst_n                     ), .hs                    (video_hs                   ), .vs                    (video_vs                   ), .de                    (video_de                   ), .rgb_r                 (video_r                    ), .rgb_g                 (video_g                    ), .rgb_b                 (video_b                    ));osd_display  osd_display_m0( .rst_n                 (rst_n                      ), .pclk                  (video_clk                  ), .i_hs                  (video_hs                   ), .i_vs                  (video_vs                   ), .i_de                  (video_de                   ), .i_data                ({video_r,video_g,video_b}  ), .o_hs                  (osd_hs                     ), .o_vs                  (osd_vs                     ), .o_de                  (osd_de                     ), .o_data                ({osd_r,osd_g,osd_b}        ));endmodule

    标签: fpga vga lcd

    上传时间: 2021-12-18

    上传用户:

  • 基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明 FPGA

    基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。module top( input                       clk, input                       rst_n, //vga output         output                      vga_out_hs, //vga horizontal synchronization          output                      vga_out_vs, //vga vertical synchronization                   output[4:0]                 vga_out_r,  //vga red output[5:0]                 vga_out_g,  //vga green output[4:0]                 vga_out_b   //vga blue );wire                            video_clk;wire                            video_hs;wire                            video_vs;wire                            video_de;wire[7:0]                       video_r;wire[7:0]                       video_g;wire[7:0]                       video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r  = video_r[7:3]; //discard low bit dataassign vga_out_g  = video_g[7:2]; //discard low bit dataassign vga_out_b  = video_b[7:3]; //discard low bit data//GENERATE video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule

    标签: fpga vga显示 verilog quartus

    上传时间: 2021-12-19

    上传用户:kingwide