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Free-FIFO

  • ISE7.1

    ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。

    标签: ISE 7.1

    上传时间: 2014-10-25

    上传用户:ruan2570406

  • xilinx公司的开放的源码

    xilinx公司的开放的源码,很有参考价值,其中有ddl,fifo控制等。

    标签: xilinx 源码

    上传时间: 2015-12-06

    上传用户:坏天使kk

  • SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C

    SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C,Quartus中将CS置低(器件地址0011010)。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用 模式,中断结合DMA方式能在NIOS II中采集和发送数据。中断信号 产生于模块中FIFO缓冲区的半满信号,读取数据端口自动清除中断 请求信号。 3、I2C IP 和FreeDev_aic23 IP分别在Quartus 工程目录中 4、SD卡读写通过SD_DAT0、SD_CLK、SD_CMD三个PIO信号线用软件 控制时序。 5、该范例读SD卡数据,通过DMA将Buffer数据送到FreeDev_aic23的 FIFO中实现数据播放。 6、SD卡中的数据必须是以48K*16bit保存的采样数据。数据可以通过SD读卡器写入。

    标签: AIC FreeDev Audio Board

    上传时间: 2013-12-09

    上传用户:aix008

  • Welcome to the software files for the ADS8361 to TMS320F2812! There are two project files in each

    Welcome to the software files for the ADS8361 to TMS320F2812! There are two project files in each of the folders McBSP, SPI and Both. Mode II and IV are explored using the McBSP port alone, as well as the SPI port. These projects are located in the SPI and McBSP folders. Modes I and III are explored using both McBSP and SPI. In Mode I, the M0 and M1 pins are controlled by use of the jumper on the evaluation module. A0 is controlled by the DX pin of the McBSP port. In Mode III, the A0, M0 and M1 pins are controlled via GPIO functions of PortF. The "SRC", "CMD" and "INCLUDE" files in the archive are from "C28x Peripheral Examples in C" (document # SPRC097). If you have questions about this or other Data Converter products, feel free to e-mail us at:

    标签: files the software Welcome

    上传时间: 2015-12-16

    上传用户:lixinxiang

  • mmsv1.2 文档

    mmsv1.2 文档,可以在open mobile alliance free download

    标签: mmsv 1.2 文档

    上传时间: 2015-12-18

    上传用户:trepb001

  • 制作UML图的小工具。 麻雀虽小五脏俱全

    制作UML图的小工具。 麻雀虽小五脏俱全,关键它是Free的

    标签: UML

    上传时间: 2014-01-07

    上传用户:hn891122

  • 使用Verilog语言编写

    使用Verilog语言编写,把FPGA配置成一个fifo

    标签: Verilog 语言 编写

    上传时间: 2015-12-25

    上传用户:xiaoxiang

  • 毕业课题部分程序: CY7C68013 Bulk IN 68013工作在AUTO IN模式

    毕业课题部分程序: CY7C68013 Bulk IN 68013工作在AUTO IN模式,16位总线 SLAVE FIFO.MASTER是 ADI BF533。

    标签: 68013 C68013 Bulk AUTO

    上传时间: 2013-12-22

    上传用户:aig85

  • The data files included are .MAT or *.dat (ASCII)files. The m-files and the data may be distributed

    The data files included are .MAT or *.dat (ASCII)files. The m-files and the data may be distributed, provided that the source is acknowledged in any publication and the data are not sold. Since this software is being distributed free of charge, the authors are not offering any technical support. Students who have any questions or difficulties using this software, or require the additional functions from the Signal Processing Toolbox should contact their professor.

    标签: files data distributed The

    上传时间: 2014-12-06

    上传用户:wuyuying

  • 移植qtopia必备库源代码

    移植qtopia必备库源代码,总共六个,分别是 e2fsprogs-1.38.tar.gz jpegsrc.v6b.tar.gz qt-embedded-2.3.10-free.tar.gz qtopia-free-source-2.1.1.tar.bz2 qt-x11-2.3.2.tar.gz tmake-1.13.tar.gz

    标签: qtopia 移植 源代码

    上传时间: 2015-12-30

    上传用户:shizhanincc