Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
标签： synchronous Designing engineer digital
上传时间： 2014-01-17
上传用户：dreamboy36
Show image on label in its full size
上传时间： 2017-07-07
上传用户：xzt
creating a finite automata
上传时间： 2017-07-16
上传用户：tedo811
two crc16 functions, one optimized for size, one optimized for speed, useful for 8-bit microprocessor
标签： optimized for microprocesso functions
上传时间： 2014-01-11
上传用户：zsjinju
study of rod with finite element method
标签： element finite method study
上传时间： 2013-11-26
上传用户：1159797854
Enlarge java script is used to enlarge a picture in to the original size, and gives the flexibility on mouse over and mouse out.
标签： flexibility the original Enlarge
上传时间： 2014-01-16
上传用户：ljmwh2000
diskfree is tools for calculate free size of disks
标签： calculate diskfree disks tools
上传时间： 2014-11-25
上传用户：蠢蠢66
Interleaved Block address generator (customized block size and interleaving strip size).
标签： size interleaving Interleaved customized
上传时间： 2014-11-28
上传用户：ardager
1-D optimal step size using golden section
标签： optimal section golden using
上传时间： 2014-12-19
上传用户：lnnn30
By using a MATLAB program, design a Delta Modulation (DM) system with one step-size and a modified DM system with two step-sizes.
标签： Modulation step-size modified program
上传时间： 2017-08-15
上传用户：LIKE
