虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

Entity-architectures

  • 各种功能的计数器实例(VHDL源代码)

    各种功能的计数器实例(VHDL源代码):ENTITY counters IS  PORT  (   d  : IN  INTEGER RANGE 0 TO 255;   clk  : IN BIT;   clear : IN BIT;   ld  : IN BIT;   enable : IN BIT;   up_down : IN BIT;   qa  : OUT  INTEGER RANGE 0 TO 255;   qb  : OUT  INTEGER RANGE 0 TO 255;   qc  : OUT  INTEGER RANGE 0 TO 255;   qd  : OUT  INTEGER RANGE 0 TO 255;   qe  : OUT  INTEGER RANGE 0 TO 255;   qf  : OUT  INTEGER RANGE 0 TO 255;   qg  : OUT  INTEGER RANGE 0 TO 255;   qh  : OUT  INTEGER RANGE 0 TO 255;   qi  : OUT  INTEGER RANGE 0 TO 255;

    标签: VHDL 计数器 源代码

    上传时间: 2014-11-30

    上传用户:半熟1994

  • CodeWarrior开发套件概述简要说明

    CodeWarrior Development Studio for ColdFire Architectures, Linux Application Edition (Classic, Linux and Windows®)

    标签: CodeWarrior 开发套件

    上传时间: 2013-10-14

    上传用户:hz07104032

  • XAPP996-双处理器参考设计套件

    This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.

    标签: XAPP 996 双处理器 参考设计

    上传时间: 2013-10-29

    上传用户:旭521

  • 移动无线终端导航AFE和数据转换器

    Abstract: High-speed and low-speed data converters serve critical functions in modern broadband mobile radios. This application note outlines how todetermine high-speed data converter performance requirements in baseband sampling radio architectures. Also, system partition strategies andadvantages are outlined when considering a high-speed analog front-end (AFE) solution.

    标签: AFE 移动 无线终端 导航

    上传时间: 2013-11-02

    上传用户:jjj0202

  • lcd计数显示程序

    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is     Port ( clk : in std_logic;      resetn : in std_logic;            dout : out std_logic_vector(7 downto 0);            lcd_en : out std_logic;            lcd_rs : out std_logic;            lcd_rw   : out std_logic); end counter;

    标签: lcd 计数显示 程序

    上传时间: 2013-10-30

    上传用户:wqxstar

  • XAPP694-从配置PROM读取用户数据

    This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.

    标签: XAPP PROM 694 读取

    上传时间: 2013-10-09

    上传用户:guojin_0704

  • WP401-FPGA设计的DO-254

    The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.

    标签: FPGA 401 254 WP

    上传时间: 2013-11-03

    上传用户:ysystc670

  • CPLD和FPGA设计介绍

    Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

    标签: CPLD FPGA

    上传时间: 2013-10-22

    上传用户:lmq0059

  • 各种功能的计数器实例(VHDL源代码)

    各种功能的计数器实例(VHDL源代码):ENTITY counters IS  PORT  (   d  : IN  INTEGER RANGE 0 TO 255;   clk  : IN BIT;   clear : IN BIT;   ld  : IN BIT;   enable : IN BIT;   up_down : IN BIT;   qa  : OUT  INTEGER RANGE 0 TO 255;   qb  : OUT  INTEGER RANGE 0 TO 255;   qc  : OUT  INTEGER RANGE 0 TO 255;   qd  : OUT  INTEGER RANGE 0 TO 255;   qe  : OUT  INTEGER RANGE 0 TO 255;   qf  : OUT  INTEGER RANGE 0 TO 255;   qg  : OUT  INTEGER RANGE 0 TO 255;   qh  : OUT  INTEGER RANGE 0 TO 255;   qi  : OUT  INTEGER RANGE 0 TO 255;

    标签: VHDL 计数器 源代码

    上传时间: 2013-10-09

    上传用户:松毓336

  • Support is available from MIPS Technologies Inc. - problems should be addressed to support@mips.co

    Support is available from MIPS Technologies Inc. - problems should be addressed to support@mips.com。This product may be controlled for export purposes. You may not export, or transfer for the purpose of reexport, any technical data received hereunder or the product produced by use of such technical data, including processes and services (the "product"), in violation of any U.S. or foreign regulation, treaty, Executive Order, law, statute, amendment or supplement thereto. Further, you may not export the product to any prohibited or embargoed country or to any denied, blocked, or designated person or entity as mentioned in any applicable U.S. or foreign regulation, treaty, Executive Order, law, statute, amendment or supplement thereto.

    标签: Technologies available addressed problems

    上传时间: 2014-01-24

    上传用户:二驱蚊器