This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sEnds the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must End by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上传时间： 2013-10-31
上传用户：yy_cn
enter——选取或启动 esc——放弃或取消 f1——启动在线帮助窗口 tab——启动浮动图件的属性窗口 pgup——放大窗口显示比例 pgdn——缩小窗口显示比例 End——刷新屏幕 del——删除点取的元件（1个） ctrl+del——删除选取的元件（2个或2个以上） x+a——取消所有被选取图件的选取状态 x——将浮动图件左右翻转 y——将浮动图件上下翻转 space——将浮动图件旋转90度 crtl+ins——将选取图件复制到编辑区里 shift+ins——将剪贴板里的图件贴到编辑区里 shift+del——将选取图件剪切放入剪贴板里 alt+backspace——恢复前一次的操作 ctrl+backspace——取消前一次的恢复 crtl+g——跳转到指定的位置 crtl+f——寻找指定的文字
上传时间： 2013-11-01
上传用户：a296386173
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intEnded for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intEnded to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from End-to-End across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-End circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
RemoteWAP is a Remote Administration Tool for any Operating System that can support the Java Virtual Machine. It has been designed for anyone who wishes to have complete control of there OS anywhere by using a WAP enabled Mobile Phone. RemoteWAP is developed using Java and WML for the client mobile phone front-End pages. RemoteWAP has a Java Swing-GUI to allow for easy control. Future releases will have a Command Line Interface for quick use
标签： Administration RemoteWAP Operating Virtual
上传时间： 2015-02-01
上传用户：exxxds
A simple utility to split a concatenated vCard format file into separate files (IETF RFC 2426 - vCard MIME Directory Profile). It splits on the BEGIN:VCARD and End:VCARD tags. It was created to help import a Lotus Organizer export file into Palm Desktop
标签： concatenated separate utility simple
上传时间： 2013-12-20
上传用户：gxf2016
c语言编程规范Style guidelines and programming practices for C/C++ code for Dynamic Software Solutions. Use the checklist at the End of this document prior to submitting code for peer review.
标签： programming guidelines Solutions for
上传时间： 2014-07-11
上传用户：aeiouetla
此代码可以实现以下功能 使用wordappalication 组件，代码如下 启动Word时用如下代码： begin try Wordapplication.Connect except MessageDlg(’Word may not be installed’, mtError, [mbOk], 0) Abort End Wordapplication.Visible := True WordApplication.Caption := ’Delphi automation’ End
标签： wordappalication 代码
上传时间： 2014-01-22
上传用户：Divine
此为编译原理实验报告 学习消除文法左递规算法，了解消除文法左递规在语法分析中的作用 内含 设计算法 目的 源码 等等.... 算法:消除左递归算法为: （1）把文法G的所有非终结符按任一种顺序排列成P1,P2,…Pn 按此顺序执行 （2）FOR i:=1 TO n DO BEGIN FOR j:=1 DO 把形如Pi→Pjγ的规则改写成 Pi→δ1γ δ2γ … δkγ。其中Pj→δ1 δ2 … δk是关于Pj的所有规则； 消除关于Pi规则的直接左递归性 End （3）化简由（2）所得的文法。即去除那些从开始符号出发永远无法到达的非终结符的 产生规则。
上传时间： 2015-03-29
上传用户：极客
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane wave source is inserted at one End. First released 12 April 1999. Version 1.03 released 2 December 1999.
标签： demonstrating stripped-down implementing minimalist
上传时间： 2013-12-21
上传用户：无聊来刷下
