Connector/Net 5.0.6 Release Notes --- --- --- Welcome to the release notes for Connector/Net 5.0.6. Important Changes --------------------- There are no major changes in this version. Please see the changelog for the list of bugs fixed.
标签： Connector Net Release Welcome
上传时间： 2013-12-16
上传用户：zyt
mysql 5.1的 jdbc驱动 Connector/J 5.1 支持Mysql 4.1、Mysql 5.0、Mysql 5.1、Mysql 6.0 alpha这些版本。 Connector/J 5.0 支持MySQL 4.1、MySQL 5.0 servers、distributed transaction (XA)。 Connector/J 3.1 支持MySQL 4.1、MySQL 5.0 servers、MySQL 5.0 except distributed transaction (XA) support。 Connector/J 3.0 支持MySQL 3.x or MySQL 4.1。
上传时间： 2014-01-03
上传用户：GHF
Java Serial Connector
上传时间： 2013-12-20
上传用户：love1314
Connector to maxdsl accounts
标签： Connector accounts maxdsl to
上传时间： 2017-06-20
上传用户：BOBOniu
connector DWGconnector DWGconnector DWGconnector DWGconnector DWG
标签： DWGconnector connector DWG
上传时间： 2017-06-24
上传用户：894898248
Printer interface with 89c51 controller (LPT Port connector)
标签： controller interface connector Printer
上传时间： 2017-08-12
上传用户：xjz632
ANSI-VITA 46.7 Ethernet on VPX Fabric Connector
标签： ANSI-VITA
上传时间： 2022-06-26
上传用户：bluedrops
确保产品之制造性, R&D在设计阶段必须遵循Layout相关规范, 以利制造单位能顺利生产, 确保产品良率, 降低因设计而重工之浪费. “PCB Layout Rule” Rev1.60 (发文字号： MT-8-2-0029)发文后, 尚有订定不足之处, 经补充修正成“PCB Layout Rule” Rev1.70. PCB Layout Rule Rev1.70, 规范内容如附件所示, 其中分为: (1) ”PCB LAYOUT 基本规范”:为R&D Layout时必须遵守的事项, 否则SMT,DIP,裁板时无法生产. (2) “锡偷LAYOUT RULE建议规范”: 加适合的锡偷可降低短路及锡球. (3) “PCB LAYOUT 建议规范”:为制造单位为提高量产良率,建议R&D在design阶段即加入PCB Layout. (4) ”零件选用建议规范”: Connector零件在未来应用逐渐广泛, 又是SMT生产时是偏移及置件不良的主因,故制造希望R&D及采购在购买异形零件时能顾虑制造的需求, 提高自动置件的比例. (5) “零件包装建议规范”:,零件taping包装时, taping的公差尺寸规范,以降低抛料率.
上传时间： 2013-04-24
上传用户：vendy
PCB Layout Rule Rev1.70, 規範內容如附件所示, 其中分為: (1) ”PCB LAYOUT 基本規範”:為R&D Layout時必須遵守的事項, 否則SMT,DIP,裁板時無法生產. (2) “錫偷LAYOUT RULE建議規範”: 加適合的錫偷可降低短路及錫球. (3) “PCB LAYOUT 建議規範”:為製造單位為提高量產良率,建議R&D在design階段即加入PCB Layout. (4) ”零件選用建議規範”: Connector零件在未來應用逐漸廣泛, 又是SMT生產時是偏移及置件不良的主因,故製造希望R&D及採購在購買異形零件時能顧慮製造的需求, 提高自動置件的比例.
上传时间： 2013-10-28
上传用户：zhtzht
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
