vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, Disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later
标签：
vhdl
编写
上传时间：
2016-05-05
上传用户：gundamwzc
