The STi7141 is a highly integrated SoC (systemon- chip) designed to meet the demanding needs of the interactive cable set top box market place. The STi7141 integrates all the major system functions into a single device, and provides world leading, multi-layer, advanced security technologies to protect valuable video and audio assets.
标签： integrated demanding designed systemon
上传时间： 2014-01-14
上传用户：894898248
This is about the USB device architecture in linux systems.
标签： architecture systems device about
上传时间： 2013-12-09
上传用户：凤临西北
ds1302 and adc conversion test program on atmega device
标签： conversion program atmega device
上传时间： 2013-10-24
上传用户：cuiyashuo
在用STVP下载程序的时候提示：the device is protected!
标签： protected device STVP the is 下载程序在用STVP下载程序的时候提示：the device is protected!
上传时间： 2017-11-11
上传用户：自动化大菜鸡
基于树莓派的Human body sensing alarm device
标签： 树莓派
上传时间： 2022-06-20
上传用户：qdxqdxqdxqdx
LPC178* 177*用户手册 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 3 — 27 December 2011 Objective data sheet
上传时间： 2013-04-24
上传用户：胡佳明胡佳明
微弱信号检测装置 四川理工学院 刘鹏飞、梁天德、曾学明 摘要： 本设计以TI的Launch Pad为核心板，采用锁相放大技术设计并制作了一套微弱信号检测装置，用以检测在强噪声背景下已知频率微弱正弦波信号的幅度值，并在液晶屏上数字显示出所测信号相应的幅度值。实验结果显示其抗干扰能力强，测量精度高。 关键词：强噪声；微弱信号；锁相放大；Launch Pad Abstract: This design is based on the Launch Pad of TI core board, using a lock-in amplifier technique designed and produced a weak signal detection device, to measure the known frequency sine wave signal amplitude values of the weak in the high noise background, and shows the measured signal amplitude of the corresponding value in the liquid crystal screen. Test results showed that it has high accuracy and strong anti-jamming capability. Keywords: weak signal detection; lock-in-amplifier; Launch Pad 1、引言 随着现代科学技术的发展，在科研与生产过程中人们越来越需要从复杂高强度的噪声中检测出有用的微弱信号，因此对微弱信号的检测成为当前科研的热点。微弱信号并不意味着信号幅度小，而是指被噪声淹没的信号，“微弱”也仅是相对于噪声而言的。只有在有效抑制噪声的条件下有选择的放大微弱信号的幅度，才能提取出有用信号。微弱信号检测技术的应用相当广泛，在生物医学、光学、电学、材料科学等相关领域显得愈发重要。 2、方案论证 针对微弱信号的检测的方法有很多，比如滤波法、取样积分器、锁相放大器等。下面就针对这几种方法做一简要说明。 方案一：滤波法。 在大部分的检测仪器中都要用到滤波方法对模拟信号进行一定的处理，例如隔离直流分量，改善信号波形，防止离散化时的波形混叠，克服噪声的不利影响，提高信噪比等。常用的噪声滤波器有：带通、带阻、高通、低通等。但是滤波方法检测信号不能用于信号频谱与噪声频谱重叠的情况，有其局限性。虽然可以对滤波器的通频带进行调节，但其噪声抑制能力有限，同时其准确性与稳定性将大打折扣。
上传时间： 2013-11-04
上传用户：lty6899826
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the device) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
上传时间： 2014-12-23
上传用户：eastimage
模拟集成电路的设计与其说是一门技术，还不如说是一门艺术。它比数字集成电路设计需要更严格的分析和更丰富的直觉。严谨坚实的理论无疑是严格分析能力的基石，而设计者的实践经验无疑是诞生丰富直觉的源泉。这也正足初学者对学习模拟集成电路设计感到困惑并难以驾驭的根本原因。.美国加州大学洛杉机分校(UCLA)Razavi教授凭借着他在美国多所著名大学执教多年的丰富教学经验和在世界知名顶级公司(AT&T，Bell Lab，HP)卓著的研究经历为我们提供了这本优秀的教材。本书自2000午出版以来得到了国内外读者的好评和青睐，被许多国际知名大学选为教科书。同时，由于原著者在世界知名顶级公司的丰富研究经历，使本书也非常适合作为CMOS模拟集成电路设计或相关领域的研究人员和工程技术人员的参考书。... 本书介绍模拟CMOS集成电路的分析与设计。从直观和严密的角度阐述了各种模拟电路的基本原理和概念，同时还阐述了在SOC中模拟电路设计遇到的新问题及电路技术的新发展。本书由浅入深，理论与实际结合，提供了大量现代工业中的设计实例。全书共18章。前10章介绍各种基本模块和运放及其频率响应和噪声。第11章至第13章介绍带隙基准、开关电容电路以及电路的非线性和失配的影响，第14、15章介绍振荡器和锁相环。第16章至18章介绍MOS器件的高阶效应及其模型、CMOS制造工艺和混合信号电路的版图与封装。 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging
上传时间： 2014-12-23
上传用户：杜莹12345
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
