联想ThinkPad老edge图纸，原理图
上传时间： 2021-11-28
上传用户：ziper
英文描述： Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs 中文描述： 双下降沿触发主从JK触发器明确和互补输出
上传时间： 2013-04-24
上传用户：黄华强
1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis\r\n2. fpga implemention of a median filter\r\n3. fpga implementation of digital filters\r\n4.hardware acceleration of edge detection algorithm on fpgas
标签： implementation reconstruction hyperspectral algorithm
上传时间： 2013-08-07
上传用户：ytulpx
One of the most critical components in a step-up design like Figure 1 is the transformer. Transformers have parasitic components that can cause them to deviate from their ideal characteristics, and the parasitic capacitance associated with the secondary can cause large resonating current spikes on the leading edge of the switch current waveform.
上传时间： 2013-11-22
上传用户：15070202241
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Contents 1 Introduction 1 2 Glosary 1 2.1 Concepts 1 2.2 Abbreviations and acronyms 4 3 Capabilities 6 4 Technical Description 6 4.1 General 6 4.2 Service oriented Allocation of Resources on the Abis interface (SARA) 8 4.3 Configuration of dedicated PDCHs in Packet Switched Domain (PSD) 10 4.4 Handling of Packet Data traffic 15 4.5 Channel selection in Cicuit Switched Domain (CSD) 19 4.6 Return of PDCHs to Cicuit Switched Domain (CSD) 22 4.7 Main changes in Ericsson GSM system R10/BSS R10 24 5 Engineering guidelines 24 6 Parameters 26 6.1 Main controlling parameters 26 6.2 Parameters for special adjustments 26 6.3 Value ranges and default values 28 7 References 29
上传时间： 2013-11-12
上传用户：ainimao
针对UHF读写器设计中，在符合EPC Gen2标准的情况下，对标签返回的高速数据进行正确解码以达到正确读取标签的要求，提出了一种新的在ARM平台下采用边沿捕获统计定时器数判断数据的方法，并对FM0编码进行解码。与传统的使用定时器定时采样高低电平的FM0解码方法相比，该解码方法可以减少定时器定时误差累积的影响；可以将捕获定时器数中断与数据判断解码相对分隔开，使得中断对解码影响很小，实现捕获与解码的同步。通过实验表明，这种方法提高了解码的效率，在160 Kb/s的接收速度下，读取一张标签的时间约为30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
上传时间： 2013-11-10
上传用户：liufei
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上传时间： 2013-10-31
上传用户：yy_cn
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-11
上传用户：gundamwzc
