The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上传时间： 2013-10-26
上传用户：yuzsu
多远程二极管温度传感器-Design Considerations for pc thermal management Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product performance and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall performance of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-programmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
标签： Considerat Design 远程 二极管
上传时间： 2014-12-21
上传用户：ljd123456
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上传时间： 2014-12-30
上传用户：aysyzxzm
When I started writing the first edition of RF Power Amplifiers for Wireless Communications,some time back in 1997, it seemed that I was roaming a largely uninhabitedlandscape. For reasons still not clear to me there were few, if any, otherbooks dedicated to the subject of RF power amplifiers. Right at the same time, however,hundreds of engineers were being assigned projects to design PAs for wirelesscommunications products. It was not, therefore, especially difficult to be successfulwith a book that was fortuitously at the right place and the right time.
标签： Communications Amplifiers Wireless Edition
上传时间： 2013-11-12
上传用户：YYRR
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
Java/J2EE application framework based on [Expert One-on-One J2EE Design and Development] by Rod Johnson. Includes JavaBeans-based configuration, an AOP framework, declarative transaction management, JDBC and Hibernate support, and a web MVC framework.
标签： Development application One-on-One framework
上传时间： 2014-01-09
上传用户：saharawalker
This model simulates a CDMA2000 1xRTT Forward link (between Base Station and Mobile Station). In particular, it simulates the Radio Configuration 3 of a Forward Fundamental channel. The block CDMA2k: Initial settings allows you to set different parameters such as data rate, Power Control SubChannel insertion rate, spreading code index, QOSF index and the channel model.
标签： Station simulates Forward between
上传时间： 2015-03-28
上传用户：13215175592
We propose and analyze several timestamping of an MPEG-2 Transport Stream transmitted strategies for performing over a packet-switched network using the PCR-unaware encapsulation scheme, and analyze their effect on the quality of the recovered clock at the MPEG-2 Systems decoder.
标签： timestamping transmitted strategies Transport
上传时间： 2014-12-05
上传用户：450976175
jboss 开发人员 手册 JBoss: A Developer s Notebook also introduces the management console, the web services messaging features, enhanced monitoring capabilities, and shows you how to improve performance. At the end of each lab, you ll find a section called "What about..." that anticipates and answers likely follow-up questions, along with a section that points you to articles and other resources if you need more information.
标签： introduces management Developer the
上传时间： 2015-04-17
上传用户：dreamboy36
