CORE

Implements a 16550/16750 UART CORE

Implements a 16550/16750 UART CORE

标签： Implements 16550 16750 UART

上传时间： 2017-06-25

上传用户：咔乐坞
Consecutive AES CORE Description of project.. Features - AES encoder - 128/192/256 bit -

Consecutive AES CORE Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added

标签： Consecutive Description AES Features

上传时间： 2017-06-25

上传用户：talenthn
HSSDRC IP CORE is the configurable universal SDRAM controller with adaptive bank control and adaptiv

HSSDRC IP CORE is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP CORE and IP CORE testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP CORE is licensed under MIT License

标签： configurable controller universal adaptive

上传时间： 2017-06-25

上传用户：皇族传媒
This is is a bridge IP CORE to interface the Tensilica PIF bus protocol with the OpenCOREs WishBone.

This is is a bridge IP CORE to interface the Tensilica PIF bus protocol with the OpenCOREs WishBone. It currently supports single-cycle as well as burst transfer operations. The CORE has been tested in a master-PIF slave-WB configuration.

标签： Tensilica OpenCOREs interface the

上传时间： 2013-12-21

上传用户：gonuiln
avr CORE porocesssor vhdl source code

avr CORE porocesssor vhdl source code

标签： porocesssor source CORE code

上传时间： 2017-06-26

上传用户：王庆才
another avr CORE porocesssor vhdl source code

another avr CORE porocesssor vhdl source code

标签： porocesssor another source CORE

上传时间： 2013-12-13

上传用户：sammi
8051 mega CORE porocesssor vhdl source code

8051 mega CORE porocesssor vhdl source code

标签： porocesssor source 8051 mega

上传时间： 2013-12-19

上传用户：diets
another 8051 CORE porocesssor vhdl source code

another 8051 CORE porocesssor vhdl source code

标签： porocesssor another source 8051

上传时间： 2014-01-25

上传用户：牧羊人8920
Quartus中实现的DDS 使用的是altera提供的IP CORE

Quartus中实现的DDS 使用的是altera提供的IP CORE

标签： Quartus altera CORE DDS

上传时间： 2017-06-27

上传用户：Breathe0125
Verilog for SPI CORE source code

Verilog for SPI CORE source code

标签： Verilog source CORE code

上传时间： 2014-01-01

上传用户：Shaikh

CORE

Implements a 16550/16750 UART CORE

Consecutive AES CORE Description of project.. Features - AES encoder - 128/192/256 bit -

HSSDRC IP CORE is the configurable universal SDRAM controller with adaptive bank control and adaptiv

This is is a bridge IP CORE to interface the Tensilica PIF bus protocol with the OpenCOREs WishBone.

avr CORE porocesssor vhdl source code

another avr CORE porocesssor vhdl source code

8051 mega CORE porocesssor vhdl source code

another 8051 CORE porocesssor vhdl source code

Quartus中实现的DDS 使用的是altera提供的IP CORE

Verilog for SPI CORE source code