This example streams input from a ADC source to a DAC. An analog signal is acquired Block-by-Block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
标签： Block-by-Block acquired example streams
上传时间： 2015-12-29
上传用户：bjgaofei
The IEEE Multipath Channel block simulates an indoor UWB channel as described in "A Channel Model for Ultrawideband Indoor Communications" by J.R. Foerster, M. Pendergrass and A.F. Molisch, November 2003, and attempts to incorporate the processes used in their MATLAB scripts.
标签： Channel Multipath simulates described
上传时间： 2015-05-08
上传用户：水中浮云
This program simulates plant identification using frequency block least mean square (FBLMS) alogrithm reference: 《LMS算法的频域快速实现》 LMS is modified by XXX in XXX place, see details in XXX relevant document
标签： identification frequency simulates alogrith
上传时间： 2016-02-29
上传用户：kytqcool
SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
标签： high-level following reference diagram
上传时间： 2013-12-15
上传用户：Miyuki
altera fpga 基于vhdl,实现vga的同步block.
上传时间： 2013-08-26
上传用户：hn891122
Protel 自定义Title Block方法
上传时间： 2014-12-24
上传用户：yl1140vista
UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用户指南
标签： LogiCORE Endpoint Block 341
上传时间： 2013-10-11
上传用户：woshinimiaoye
7.4 基于IP CORE的BLOCK RAM设计修改稿。
上传时间： 2013-11-07
上传用户：sammi
Protel 自定义Title Block方法
上传时间： 2015-01-01
上传用户：黄华强
UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用户指南
标签： LogiCORE Endpoint Block 341
上传时间： 2013-10-17
上传用户：jeffery
