这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－Bench等文件。
标签： 255
上传时间： 2015-07-18
上传用户：wendy15
encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-Bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license
标签： Berlekamp berlekamp algorithm generator
上传时间： 2014-02-16
上传用户：fxf126@126.com
HDL实现的DES算法，及相关的Test Bench激励文件
上传时间： 2015-09-21
上传用户：sk5201314
The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bitstream File 2) Sram_Interface.ucf -----------------> UCF File 3) Sram_Interface.vhd -----------------> Main Entity 4) Sram_Interface_tb.vhd ------------> Test Bench 5) SRAM_RD_WR.vhd ------------> Sub Module
标签： Sram_Interface following Hardware contains
上传时间： 2014-11-11
上传用户：gmh1314
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test Bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
标签： Development Startix2 tailored Altera
上传时间： 2014-01-19
上传用户：chongcongying
基于 xinlinx 写的DES加密算法，内涵test Bench，加密解密都有
上传时间： 2016-01-04
上传用户：dreamboy36
计数器 锁存器 12位寄存器 带load，clr等功能的寄存器 双向脚（clocked bidirectional pin） 一个简单的状态机 一个同步状态机 用状态机设计的交通灯控制器 数据接口 一个简单的UART 测试向量（Test Bench）举例： 加法器源程序 相应加法器的测试向量test Bench）
上传时间： 2014-01-16
上传用户：bjgaofei
作为数字集成电路的硬件工程师，在做设计的时候，写Test Bench是很重要的，甚至重要过你的一些设计本身，因为它可以确定你的设计是否可用可行，并且能够优化你的设计。
上传时间： 2014-01-01
上传用户：ggwz258
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test Bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting
标签： synthesizable microcontro Synthetic PIC
上传时间： 2013-12-22
上传用户：妄想演绎师
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test Bench available. This core is very simple and is proven in hardware. I see no point of writing a test Bench at this time.
标签： conversion Includes parallel stuffing
上传时间： 2017-03-11
上传用户：hn891122
