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  • This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab co

    This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to Be generated based on an input data file. The data can Be random data, a grey scale image, a wave file, or any type of file. The generated OFDM signal is stored as a windows wave file, allowing it to Be viewed, listened to and manipulated in other programs. The modified wave file can then Be decoded by the receiver software to extract the original data. This code was developed for the experiments that I performed in my honours thesis, and thus has not Been fully debugged. This is the original code developed for the thesis and so has several problems with it. The BeR performance given by the simulations is infact Symbol Error Rate.

    标签: This measurements practical section

    上传时间: 2015-09-20

    上传用户:tedo811

  • There is an example of how to use the LDPC encode/decode with AWGN channel model in files .ldpc_de

    There is an example of how to use the LDPC encode/decode with AWGN channel model in files .\ldpc_decode.m and .\GFq\ldpc_decode.m. There are a few parity check matrices available in the code but you can use other matrices provided you have enough memory to load them. I suggest checking out matrices in Alist format available on David MacKay s web site.You will need to have access to a MEX compiler to Be able to use a few functions written in C. LDPC的仿真代码

    标签: example channel ldpc_de encode

    上传时间: 2013-12-03

    上传用户:lili123

  • Problem Statement You are given a string input. You are to find the longest substring of input su

    Problem Statement You are given a string input. You are to find the longest substring of input such that the reversal of the substring is also a substring of input. In case of a tie, return the string that occurs earliest in input. Definition Class: ReverseSubstring Method: findReversed Parameters: string Returns: string Method signature: string findReversed(string input) (Be sure your method is public) Notes The substring and its reversal may overlap partially or completely. The entire original string is itself a valid substring (see example 4). Constraints input will contain Between 1 and 50 characters, inclusive. Each character of input will Be an uppercase letter ( A - Z ). Examples 0) "XBCDEFYWFEDCBZ" Returns: "BCDEF" We see that the reverse of BCDEF is FEDCB, which appears later in the string. 1)

    标签: input Statement You are

    上传时间: 2015-09-21

    上传用户:sunjet

  • If we have two individually sorted vectors "a" and "b" but they are not sorted with respect to each

    If we have two individually sorted vectors "a" and "b" but they are not sorted with respect to each other and we want to merge them into vector "c" such that "c" is also a sorted vector. Then c=mergesorted(a,b) can Be used.

    标签: sorted individually respect vectors

    上传时间: 2015-09-23

    上传用户:comua

  • Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary

    Two functions, num2bin and bin2num are provided. num2bin takes a double and converts it to a binary string representation. bin2num is its inverse operation. It can Be used in a numerical analysis course when floating point arithmetic is discussed.

    标签: num2bin functions and converts

    上传时间: 2014-01-07

    上传用户:gdgzhym

  • * "Copyright (c) 2006 RoBert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.

    * "Copyright (c) 2006 RoBert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.msstate.edu, Mississippi State University) * IN NO EVENT SHALL THE "AUTHOR" Be LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHOR" * HAS BeEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

    标签: Reese B. R. Copyright

    上传时间: 2015-09-24

    上传用户:mpquest

  • Verilog and VHDL状态机设计

    Verilog and VHDL状态机设计,英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will Be 2.0 Basic HDL coding presented. Different methodologies will Be compared using real-world examples.

    标签: Verilog VHDL and 状态

    上传时间: 2013-12-19

    上传用户:change0329

  • This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a

    This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a decimal array that can Be used within typical .m file coding.

    标签: polynomial primitive converts created

    上传时间: 2015-09-26

    上传用户:wang5829

  • This getting started exercise will guide you through the step-by-step process of transforming a MATL

    This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can Be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.

    标签: step-by-step transforming exercise getting

    上传时间: 2014-01-17

    上传用户:VRMMO

  • Often it is necessary to add some logical control to a MATLAB algorithm to allow the generated hardw

    Often it is necessary to add some logical control to a MATLAB algorithm to allow the generated hardware to function correctly in the overall system. This lab exercise will explore how hardware control can Be added to a MATLAB algorithm and synthesized using AccelDSP Synthesis.

    标签: algorithm generated necessary to

    上传时间: 2014-01-25

    上传用户:yimoney