cordic IC implement for fast cordic calculate. Including test BENCH. feature: 1. slicon proved. 2. support angle recored algorithm.
标签： cordic calculate Including implement
上传时间： 2017-01-06
上传用户：270189020
test BENCH for spi communication
标签： communication BENCH test for
上传时间： 2017-04-25
上传用户：zm7516678
TEst BENCH of an increment date
上传时间： 2017-04-27
上传用户：colinal
Test BENCH for an engine code VHDL for CY7C1062AV33
上传时间： 2017-04-27
上传用户：tfyt
Test BENCH for CY7C1062AV33
上传时间： 2014-12-07
上传用户：lingzhichao
Pure hardware JPEG Encoder design. Package includes vhdl source code, test BENCH, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
标签： design hardware includes Encoder
上传时间： 2013-12-15
上传用户：王者A
怎样编写仿真功能的测试文件（test BENCH）
上传时间： 2014-11-17
上传用户：磊子226
介绍一种基于C8051F060单片机和NAND Flash的数据采集存储系统，该系统可实现3路信号采样，每路采样率为5KS/s,通过异步串行通信接口实现数据传输。并详细说明系统的软件设计。 Abstract: An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to sample three-channel of signal,5KSPS each channel,and can upload data to test BENCH through UART（Universal Asynchronous Receiver/Transmitter）.The software design is discussed in detail.
上传时间： 2013-10-12
上传用户：Jesse_嘉伟
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL TestBENCH files. This files only include the testBENCH behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test BENCH for txmit.vhd. rcvr_tf.vhd -- Test BENCH for rcvr.vhd.
上传时间： 2013-11-07
上传用户：jasson5678
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL TestBENCH files. This files only include the testBENCH behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test BENCH for txmit.vhd. rcvr_tf.vhd -- Test BENCH for rcvr.vhd.
上传时间： 2013-11-02
上传用户：18862121743
