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Asynchronous

  • Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availabilit

    Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double Asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.

    标签: connectivity applications availabilit nanoWatt

    上传时间: 2016-02-04

    上传用户:CHINA526

  • 本人收集的ajax一些资料

    本人收集的ajax一些资料,打印版。 Ajax这个概念的最早提出者Jesse James Garrett认为:   Ajax是Asynchronous JavaScript and XML的缩写。   Ajax并不是一门新的语言或技术,它实际上是几项技术按一定的方式组合在一在同共的协作中发挥各自的作用,它包括   使用XHTML和CSS标准化呈现   使用DOM实现动态显示和交互   使用XML和XSLT进行数据交换与处理   使用XMLHttpRequest进行异步数据读取   最后用JavaScript绑定和处理所有数据 谢谢大家

    标签: ajax

    上传时间: 2013-12-15

    上传用户:c12228

  • A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full asyn

    A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full Asynchronous HW/SW crypto acceleration to the Linux kernel, OpenSwan, OpenSSL and applications using DES, 3DES, AES, MD5, SHA, PublicKey, RNGs and more.

    标签: port Cryptographic Framework FreeBSD

    上传时间: 2016-03-29

    上传用户:小宝爱考拉

  • vhdl编写

    vhdl编写,8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later

    标签: vhdl 编写

    上传时间: 2016-05-05

    上传用户:gundamwzc

  • CRC码产生器与校验器程序 Features : Executes in one clock cycle per data word Any polynomial from 4 to 32 b

    CRC码产生器与校验器程序 Features : Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or Asynchronous reset

    标签: polynomial Features Executes clock

    上传时间: 2013-12-18

    上传用户:Ants

  • 基于AJAX的动态树型结构的设计与实现 简要介绍了一种通用的

    基于AJAX的动态树型结构的设计与实现 简要介绍了一种通用的,动态树型结构的实现方案,该方案基于Asynchronous JavaScript and XML,结合Struts框架设计实现了结构清晰、扩展性良好的多层架构,数据存储于数据库,结合XML描述树的节点信息,使得任何按预定的XML文档描述的信息都可以通过动态树来展现。

    标签: AJAX 动态

    上传时间: 2016-12-22

    上传用户:爱死爱死

  • Serial UART open source core. The design is engineered for use as a stand alone chip or for use with

    Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that Asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.

    标签: engineered for use Serial

    上传时间: 2017-03-11

    上传用户:aa17807091

  • The use of hardware description languages (HDLs) is becoming increasingly common for designing and

    The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).

    标签: increasingly description designing languages

    上传时间: 2014-01-08

    上传用户:小草123

  • The objective of this project is to create a driver for a camera module (we used the OV7620). After

    The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external Asynchronous RAM, and then send it to the computer through a serial cable

    标签: objective project create camera

    上传时间: 2017-09-11

    上传用户:远远ssad

  • 基于TMS320F28035芯片为控制核心的空间矢量异步电机变频器

    基于TMS320F28035芯片为控制核心的空间矢量异步电机变频器  我们设计的异步电机变频调速器以TMS320F28035芯片为控制核心,通过输出三相PWM波控制智能功率模块IPM驱动三相异步电机。我们使用空间矢量SVPWM算法,并对其进行了优化。采用检测反电势的方法省去了昂贵的光电编码器,大大节省了成本。同时开创性的研发了自动根据运行环境调节的自适应变频算法,使我们的变频调速器可以在电网条件恶劣的乡村山区工作,由此该变频器已被一家民用水泵生产企业预订。关键字 变频器 TMS320f28035 IPM SVPWM In our design, the Asynchronous machine inverter based on the chip of TMS320F28035 drives the three-Phase Asynchronous machine by sending three-phase PWM waves to the IPM, which is short for the Intelligent-Power-Module. The SVPWM (space vector pulse width modulation) strategy is applied to our control algorithm and we optimize it mainly in two aspects. Firstly the inverter detects the speed by measuring the Back EMF instead of installing an expensive photoelectric encoder for costs reduction. 

    标签: tms320f28035 芯片

    上传时间: 2022-05-08

    上传用户:zhanglei193