Advanced Asic Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and
techniques used towards Asic chip synthesis, physical synthesis, formal
verification and static timing analysis, using the Synopsys suite of tools.
High volume USB 2.0 devices will be designed using Asic technology with embedded USB 2.0 support.
For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled
in a vendors VHDL code, with the Asic vendor providing only a simple level translator to meet the USB
signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0
signaling running at hundreds of MHz, the existing design methodology must change.
