The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An ACtive LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上传时间： 2014-11-22
上传用户：xcy122677
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (ACtive HIGH or ACtive LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上传时间： 2013-11-13
上传用户：fredguo
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An ACtive LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上传时间： 2013-10-13
上传用户：bakdesec
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the ACtive HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
上传时间： 2014-01-18
上传用户：bs2005
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-ACtive noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
标签： MULTICHANNEL 5.5 TO RS
上传时间： 2013-10-19
上传用户：ddddddd
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the ACtive downstream channels, and devices on the ACtive downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上传时间： 2013-10-11
上传用户：dianxin61
本文简单介绍了MCGS 组态软件和SPCE061A 单片机的特点，即北京昆仑通态自动化软件科技有限公司的工控组态软件MCGS(Monitor and Control Generated System )和台湾凌阳科技推出的16 位微控制器SPCE061A，重点介绍了如何一步步开发SPCE061A 单片机的驱动程序，并简单介绍了下位机程序的设计，最后给出了测试情况。计算机技术的飞速发展为工业自动化开辟了广阔的发展空间，人们可以快捷地开发和组建高效的控制系统。笔者设计的液体点滴监控模型,可以对液体点滴情况实现远程监控和现场监控，终端和上位机均可人工设定所需的液体点滴速度并动态显示。在这方面，MCGS 工控组态软件提供了强有力的支持，它是一套Windows 环境下快速构造和生成上位机监控系统的组态软件系统，可快速构造和生成数据采集、报警处理、流程控制、动画显示、报表输出等界面,实现各种工程曲线的绘制、报表输出、远程通信等功能 [1]。MCGS 作为一种方便有效的通用工控软件,它提供了国内外各种常用的工控设备的驱动程序。但在实际应用中,因为所用设备的特殊性,允许用户根据需要来定制设备驱动程序。MCGS 用ACtive DLL 构件实现设备驱动程序,通过规范的OLE 接口挂接到MCGS 中,使其构成一个整体。鉴于Visual Basic 语言的通用性和简单性,使用VB 来开发单片机驱动,MCGS 的实现方法和原理与标准的ACtive DLL 完全一致,但MCGS 规定了一套接口规范,只有遵守这些接口规范的ACtive DLL 才能用作MCGS 的设备驱动构件。利用具有语音和 DSP 功能的SPCE061A 单片机作为液体点滴监控模型的核心控制器，SPCE061A 是台湾凌阳科技推出的16 位微控制器，提供了丰富的软、硬件资源，开发灵活方便。除此之外SPCE061A 的最高时钟频率可达到49MHz,具有运算速度高的优势，这为语音的录制和播放提供了条件[4]。
上传时间： 2013-12-19
上传用户：leesuper
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anACtive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上传时间： 2014-01-24
上传用户：xinhaoshan2016
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is ACtive low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上传时间： 2013-10-31
上传用户：yy_cn
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anACtive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上传时间： 2013-11-19
上传用户：m62383408
