Abstract: This application note describes how to design boost converters using the MAX17597 peakcurrent-mode controller. Boost converters can be operated in discontinuous conduction mode (DCM) orcontinuous conduction mode (CCM). This operating mode can affect the component choices, stress levelin power devices, and controller design. Formulas for calculating component values and ratingsare alsopresented.
上传时间： 2013-11-16
上传用户：zcs023047
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上传时间： 2013-10-25
上传用户：banyou
数字校准技术
上传时间： 2013-10-26
上传用户：qiaoyue
８位高速AD转换器TLC5510的应用
上传时间： 2013-12-16
上传用户：sc965382896
本设计通过采用分割电容阵列对DAC进行优化，在减小了D/A转换开关消耗的能量、提高速度的基础上，实现了一款采样速度为1 MS/s的10-bit单端逐次逼近型模数转换器。使用cadence spectre 工具进行仿真，仿真结果表明，设计的D/A转换器和比较器等电路满足10-bit A/D 转换的要求，逐次逼近A/D转换器可以正常工作。
上传时间： 2013-11-21
上传用户：chukeey
Abstract: This design idea explains how to implement an 8-bit analog-to-digital converter (ADC), using a microcontroller
上传时间： 2013-10-30
上传用户：爱死爱死
设计由555、移位寄存器、D/A转换器、PLD等器件构成的多路序列信号输出和阶梯波输出的发生器电路，重点学习555、D/A转换器及可编程逻辑器件的原理及应用方法。用Proteus软件仿真；实验测试技术指标及功能、绘制信号波形。
上传时间： 2013-11-03
上传用户：crazyer
ad转换器
上传时间： 2014-12-23
上传用户：Bert520
Abstract: Specifications such as noise, effective number of bits (ENOB), effective resolution, and noise-free resolution inlarge part define how accurate an ADC really is. Consequently, understanding the performance metrics related to noise isone of the most difficult aspects of transitioning from a SAR to a delta-sigma ADC. With the current demand for higherresolution, designers must develop a better understanding of ADC noise, ENOB, effective resolution, and signal-to-noiseratio (SNR). This application note helps that understanding.
上传时间： 2013-10-16
上传用户：x18010875091
如果明智地选择时钟，一份简单的抖动规范几乎是不够的。而重要的是，你要知道时钟噪声的带宽和频谱形状，才能在采样过程中适当地将它们考虑进去。很多系统设计师对数据转换器时钟的相位噪声和抖动要求规定得不够高，几皮秒的时钟抖动很快就转换成信号路径上的数分贝损耗。
上传时间： 2014-12-23
上传用户：dreamboy36
