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it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

资源大小：32 K
上传时间： 2014-06-26
上传用户：ll122644144
资源积分：2 下载积分
标签： synthesize simulator modelsim verilog

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it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.

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您现在的位置是：虫虫下载站 > 资源下载 > VHDL/FPGA/Verilog > it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

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