Bluetooth IP CORE .very goog as a study file .
资源简介:Bluetooth IP CORE .very goog as a study file .
上传时间: 2014-12-06
上传用户:dbs012280
资源简介:AVR_CORE IP CORE .very GOOD AS A study FILE
上传时间: 2013-12-19
上传用户:lanwei
资源简介:can IP CORE .very GOOD AS A study FILE
上传时间: 2013-12-21
上传用户:yimoney
资源简介:Embedded_risc IP CORE .very GOOD AS A study FILE
上传时间: 2014-01-17
上传用户:JasonC
资源简介:keyboardcontroller IP CORE .very GOOD AS A study FILE
上传时间: 2013-12-20
上传用户:LIKE
资源简介:IP CORE .very GOOD AS A study FILE
上传时间: 2014-06-19
上传用户:dongbaobao
资源简介:IP CORE .very GOOD AS A study FILE
上传时间: 2017-01-31
上传用户:lifangyuan12
资源简介:USB IP CORE.very good
上传时间: 2013-12-17
上传用户:邶刖
资源简介:Implements layered decoding using the sum-product-algorithm. Codes are input as a .txt file in A-list format.
上传时间: 2014-12-01
上传用户:WMC_geophy
资源简介:Programs for extracting FIC and MSC data from real broadcasted ensemble recorded as a data file.
上传时间: 2017-07-06
上传用户:大融融rr
资源简介:The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP CORE) in a VHDL simulation environment. The CORE is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of...
上传时间: 2016-02-16
上传用户:wcl168881111111
资源简介:Serial UART open source CORE. The design is engineered for use as a stand alone chip or for use with other of our COREs. The reason for developing the Serial UART CORE is the fact, that asynchronous serial communication is very common that ...
上传时间: 2017-03-11
上传用户:aa17807091
资源简介:This is is a bridge IP CORE to interface the Tensilica PIF bus protocol with the OpenCOREs WishBone. It currently supports single-cycle as well as burst transfer operations. The CORE has been tested in a master-PIF slave-WB configuration.
上传时间: 2013-12-21
上传用户:gonuiln
资源简介:free hardware ip CORE about sparcv8,a soc cpu in vhdl
上传时间: 2015-11-10
上传用户:xsnjzljj
资源简介:《Learning C++ as a new language》is a very good book.
上传时间: 2013-12-23
上传用户:363186
资源简介:a very goog book
上传时间: 2016-07-27
上传用户:jennyzai
资源简介:Raggedstone1 IP CORE. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
上传时间: 2013-12-02
上传用户:lps11188
资源简介:This software package contains the USB framework CORE developped by ATMEL, as well as a CDC driver for an USB to serial converter. The following files are included : - CORE/ -> Source code for the framework CORE -> Makefile for ...
上传时间: 2017-02-14
上传用户:qq1604324866
资源简介:This software package contains the USB framework CORE developped by ATMEL, as well as a Mass storage driver. The MSD driver uses the internal flash of the chip to operate as a disk-on-key. The following files are included : - CORE/ ...
上传时间: 2017-02-14
上传用户:003030
资源简介:Video-DVM is a very cheap DVM that shows how an output as complex as a videocomposite signal can be generated entirely in software: two I/O pins and three resistors are all the hardware required. Connected to any TV set it displays voltages...
上传时间: 2014-12-09
上传用户:xuan‘nian
资源简介:USBHostSlave is a USB 1.1 host and Device IP CORE. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer...
上传时间: 2014-01-17
上传用户:sxdtlqqjl
资源简介:This book provide a very timely introduction to the concepts of USB as well as a very practical guide on how to design USB peripheral products.
上传时间: 2013-12-20
上传用户:eclipse
资源简介:aiNet application is a very powerful and a very simple tool for solving the problems which are usually solved with artificial neural networks (ANN). All possible tests we had run proved that the results obtained with aiNet are at least as g...
上传时间: 2014-01-16
上传用户:wang5829
资源简介:Run Pac-man Game Based on 8086/8088 FPGA IP CORE
上传时间: 2013-08-23
上传用户:JamesB
资源简介:Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, ...
上传时间: 2013-09-25
上传用户:baiom
资源简介:PCI总线是目前最为流行的一种局部性总线 通过对PCI总线一些典型功能的分析以及时序的阐述,利用VetilogHDL设计了一个将非PCI功能设备转接到PC1总线上的IP CORE 同时,通过在ModeISim SE PLUS 6.0 上运行测试程序模块,得到了理想的仿真数据波形,从软件上证...
上传时间: 2014-12-30
上传用户:himbly
资源简介:7.4 基于IP CORE的BLOCK RAM设计修改稿。
上传时间: 2013-11-07
上传用户:sammi
资源简介:Learning Standard C++ as a New Language
上传时间: 2015-02-25
上传用户:libenshu01
资源简介:USB 1.1 IP-CORE和设计范例 VHDL源代码
上传时间: 2013-12-19
上传用户:mikesering
资源简介:VHDL ip CORE的设计,软核的设计方法
上传时间: 2015-03-09
上传用户:爺的气质