verilog spi file with testbench
资源简介:verilog spi file with testbench
上传时间: 2013-12-26
上传用户:电子世界
资源简介:verilog ADPLL file with testbench.v
上传时间: 2015-07-09
上传用户:cx111111
资源简介:verilog ADPLL file with testbench
上传时间: 2013-12-01
上传用户:yulg
资源简介:verilog vcspi file with testbench
上传时间: 2016-11-05
上传用户:784533221
资源简介:verilog ADPLL file with testbench
上传时间: 2016-11-05
上传用户:wmwai1314
资源简介:This zip describes SPI communication with a Serial DataFlash AT45DB and/or with a DataFlashCard AT45DCB. It shows how to configure the SPI peripheral on the AT91RM9200EK. Includes main.html file for help. For use under Green Hills 3.6.1 Mul...
上传时间: 2015-05-24
上传用户:lvzhr
资源简介:midi file with midi play.it can run in the computer
上传时间: 2013-12-12
上传用户:aig85
资源简介:this a rsa example to encrypt file with RSA
上传时间: 2016-01-08
上传用户:ljt101007
资源简介:Solve Sudoku(Game) quickly. Just need a txt file with all of the number u have, then answer out.
上传时间: 2016-01-30
上传用户:gonuiln
资源简介:AN485_CH-MAX II CPLD 中的串行外设接口主机(verilog SPI)
上传时间: 2013-12-14
上传用户:zl5712176
资源简介:FCP takes a file, generates a random 2048 bit key and encrypts the file with a RC4 stream cipher. The encrypted file is written to a new file along with the decryption stub and key. When the output file is executed it decrypts and execu...
上传时间: 2013-12-08
上传用户:爺的气质
资源简介:verilog test file not vhd
上传时间: 2017-05-03
上传用户:啊飒飒大师的
资源简介:MAC-4bit verilog source code with CSA style
上传时间: 2014-01-13
上传用户:小码农lz
资源简介:verilog SPI 源码(来自网络)
上传时间: 2017-07-11
上传用户:z754970244
资源简介:verilog quick guide with lots of helpful tips and tricks
上传时间: 2014-01-24
上传用户:Amygdala
资源简介:Simple shift register with testbench in vhdl
上传时间: 2017-08-20
上传用户:lingzhichao
资源简介:this is hupffman code.you can compress file with this application
上传时间: 2017-09-08
上传用户:skhlm
资源简介:ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and printed both to the console and to an output file. • Assume a file with correct data (no garbage, characters, etc.). • you must ch...
上传时间: 2014-08-30
上传用户:dsgkjgkjg
资源简介:This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. ...
上传时间: 2014-01-19
上传用户:chongcongying
资源简介:This is a program to extract the drum sounds (bass) from a music file. You can replace the "windycity.wav" file with any other .wav file you want.
上传时间: 2017-06-25
上传用户:cc1915
资源简介:This m file hide an image jpeg,png in another jpeg,png image. The height and width of the secret image is in LSB of 1st 32 pixels of 1st row of the cover image.This helps in the recovery of secret image. The secret image must be...
上传时间: 2017-07-25
上传用户:gououo
资源简介:如果用户现有的是 Protel99SE 。ProtelDXP,Protel2004 版本: 1 在powerpcb 软件的中打开 PCB 文件,选择导出 ASCII 文件(export ascii file) ,ascii file 的版本应该选择 3.5 及以下的版本。 2 a 在 Protel99SE 。ProtelDXP , 选择 ...
上传时间: 2013-10-16
上传用户:whymatalab
资源简介:工具分类:攻击程序 运行平台:Windows 工具大小:7577 Bytes 文件MD5 :28f6d5f4d818438522a3d0dc8a3fa46b 工具来源:securiteam.com // GDI+ buffer overrun exploit by FoToZ // NB: the headers here are only sample headers taken from a .JPG file, //...
上传时间: 2015-01-20
上传用户:Late_Li
资源简介:在逻辑的系统仿真中使用的FLASH模型(AMD的Am29lv160d),包括VHDL代码文件和verilog代码文件和testbench,并且有相应的pdf说明文档。
上传时间: 2017-02-20
上传用户:zhanditian
资源简介:This document describes the interface between HLA and Linux via direct system calls. The HLA Standard Library provides a header file with a set of important constants, data types, and procedure prototypes that you can use to make Linux sy...
上传时间: 2013-12-24
上传用户:shus521
资源简介:This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
上传时间: 2014-01-15
上传用户:wuyuying
资源简介:RealView Developer Suite v2.2 破解 (2009-12-11) 使用RealView Developer Suite v2.2,传说中的RVDS 2.2,破解也有问题,经过我琢磨。 破解步骤修改如下: 1)用generate产生license file (注意自己的系统时间 最好是真实的当前时间,如果时间比...
上传时间: 2017-01-18
上传用户:zbxinu
资源简介:DAC converter design with verilog code and testbench
上传时间: 2014-01-23
上传用户:yyyyyyyyyy
资源简介:A clock writing by verilog which can count from 00:00 to 23:59. with a C file to see the simulation results. A co-design example of C and verilog.
上传时间: 2016-10-12
上传用户:王者A
资源简介:A code writing by verilog which can find medium value. with a C file to see the simulation results. A co-design example of C and verilog.
上传时间: 2014-11-18
上传用户:ljt101007