The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-PERFORMANCE, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-PERFORMANCE RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
标签： MIPS 8482 Technologies 174
上传时间： 2014-12-22
上传用户：semi1981
螺旋桨PID控制 In response to constant pressure to design more efficient, faster, smaller, and better systems, engineers are constantly looking for ways to improve existing designs or replace them with better ones. Facing large fuel costs, the aerospace industry in particular has been researching alternative designs to increase fuel efficiency and PERFORMANCE. One such alternative is the development of reconfigurable aircraft wings. These wings would be able to adapt to the current environment increasing lift or reducing drag when appropriate.
标签： efficient response constant pressure
上传时间： 2016-11-22
上传用户：trepb001
The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-PERFORMANCE benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the PERFORMANCE of different computers or, in this case, the efficiency of the code generated for the same computer by different compilers. The test reports general PERFORMANCE in dhrystones per second. Like most benchmark programs, dhrystone consists of standard code and concentrates on string handling. It uses no floating-point operations. It is heavily influenced by hardware and software design, compiler and linker options, code optimizing, cache memory, wait states, and integer data types. The DHRY program is available in different targets: Simulator: Large Model: DHRY example in LARGE model for Simulation Philips 80C51MX: DHRY example in LARGE model for the Philips 80C51MC
标签： general-performanc benchmarks Dhrystone dhrystone
上传时间： 2016-11-30
上传用户：hphh
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-PERFORMANCE processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing PERFORMANCE (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features.
标签： TMS 320 generation 240
上传时间： 2013-12-16
上传用户：GavinNeko
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz PERFORMANCE with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
ucos2 is a file system for embedded applications which can be used on any media, for which you can provide basic hardware access functions. µ C/FS is a high PERFORMANCE library that has been optimized for minimum memory consumption in RAM and ROM, high speed and versatility. It is written in ANSI C and can be used on any CPU.
标签： which applications can for
上传时间： 2017-01-04
上传用户：偷心的海盗
ucos2 is a file system for embedded applications which can be used on any media, for which you can provide basic hardware access functions. µ C/FS is a high PERFORMANCE library that has been optimized for minimum memory consumption in RAM and ROM, high speed and versatility. It is written in ANSI C and can be used on any CPU.
标签： which applications can for
上传时间： 2017-01-04
上传用户：13517191407
The exercise should be finished in English. 2. According to Prof. Zhang s requirement, this exercise mainly focuses on the BER PERFORMANCE of some wireless communication system using specific coding and modulation type through the AWGN channel. Signal-to-Noise ration (SNR) varies from 5dB to 20dB.
标签： requirement According exercise finished
上传时间： 2014-01-06
上传用户：zhangyigenius
Unix Unleashed, Third Edition is written with the power user and system administrator in mind. This book will help the reader understand the nuances of the major Unix variants including SVR4, HP-UX, Solaris, AIX, BSD, IRIX, SunOS, and Linux. It will help the reader decide which Unix shell works best for their particular situation. Other topics such as Kernel Configuration, Networking, User Administration, and File Management are covered extensively for the administrator who wants a variety of options to choose from for best PERFORMANCE. The book also provides in-depth coverage of configuring and optimizing mail, DNS, HTTP and other services many companies deploy across their intranet and on the Internet
标签： administrator Unleashed Edition written
上传时间： 2017-01-13
上传用户：来茴
This paper studies the problem of tracking a ballistic object in the reentry phase by processing radar measurements. A suitable (highly nonlinear) model of target motion is developed and the theoretical Cramer—Rao lower bounds (CRLB) of estimation error are derived. The estimation PERFORMANCE (error mean and
标签： processing ballistic the tracking
上传时间： 2014-10-31
上传用户：yyyyyyyyyy
