verilog实现I2C通信的slave模块源码状态机设位计可做I2C接口的仿真模型
//`timescale 1ns/1ps
module I2C_slv (
input [6:0] slv_id,
input RESET,
input scl_i, //I2C clk
input sda_i, //I2C data in
input [7:0] I2C_RDDATA,
////////////////////////
output reg sda_o, //I2C data out
output reg reg_w, //reg write enable pulse (1T of scl_i)
output reg [7:0] I2C_ADDR,
output reg [7:0] I2C_DATA
);
parameter ST_ADDR = 4'd0;
parameter ST_ACK = 4'd1;
parameter ST_WDATA1 = 4'd2;
parameter ST_WACK1 = 4'd3;
parameter ST_WDATA2 = 4'd4;
parameter ST_WACK2 = 4'd5;
parameter ST_WDATA3 = 4'd6;
parameter ST_WACK3 = 4'd7;
parameter ST_RDATA1 = 4'd8;
parameter ST_RACK1 = 4'd9;
parameter ST_IDLE = 4'd15;
//---------------------------------------------------------------------------
// Signal Declaration
//---------------------------------------------------------------------------
reg i2c_start_n, i2c_stop_n;
//wire RESET_scl;
wire i2c_stp_n, i2c_RESET;
reg [3:0] i2c_cs, i2c_ns;
reg [3:0] cnt_bit;
reg [7:0] d_vec;
reg i2c_rd, i2c_ack;
reg [7:0] I2C_RDDATA_latch;
